XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 3

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS099-1 (v2.5) December 4, 2009
Introduction
The Spartan
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
five million system gates, as shown in
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving
enhancements derive from the Virtex
ogy. These Spartan-3 FPGA enhancements, combined with
advanced process technology, deliver more functionality
and bandwidth per dollar than was previously possible, set-
ting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Table 1: Summary of Spartan-3 FPGA Attributes
Notes:
1.
2.
© 2003–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS099-1 (v2.5) December 4, 2009
Product Specification
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Device
Logic Cell = 4-input Look-Up Table (LUT) plus a ‘D’ flip-flop. "Equivalent Logic Cells" equals "Total CLBs" x 8 Logic Cells/CLB x 1.125 effectiveness.
These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family.
(2)
(2)
(2)
(2)
clock
®
-3 family of Field-Programmable Gate Arrays
System
Gates
200K
400K
1.5M
50K
1M
2M
4M
5M
management
Equivalent
Cells
17,280
29,952
46,080
62,208
74,880
1,728
4,320
8,064
Logic
(1)
R
Rows Columns
104
16
24
32
48
64
80
96
(One CLB = Four Slices)
functions.
®
Table
-II platform technol-
CLB Array
12
20
28
40
52
64
72
80
1.
Numerous
1,920
3,328
5,120
6,912
8,320
CLBs
Total
192
480
896
10
0
www.xilinx.com
0
Distributed
RAM Bits
(K=1024)
120K
208K
320K
432K
520K
12K
30K
56K
Spartan-3 FPGA Family:
Introduction and Ordering
Information
Product Specification
Features
•
•
•
•
•
•
•
•
•
•
Low-cost, high-performance logic solution for high-volume,
consumer-oriented applications
-
SelectIO™ interface signaling
-
-
-
-
-
-
-
-
Logic resources
-
-
-
-
-
SelectRAM™ hierarchical memory
-
-
Digital Clock Manager (up to four DCMs)
-
-
-
Eight global clock lines and abundant routing
Fully supported by
software development systems
MicroBlaze™ and PicoBlaze™ processor,
Express
Pb-free packaging options
Automotive
Densities up to 74,880 logic cells
Up to 633 I/O pins
622+ Mb/s data transfer rate per I/O
18 single-ended signal standards
8 differential I/O standards including LVDS, RSDS
Termination by Digitally Controlled Impedance
Signal swing ranging from 1.14V to 3.465V
Double Data Rate (DDR) support
DDR, DDR2 SDRAM support
Abundant logic cells with shift register capability
Wide, fast multiplexers
Fast look-ahead carry logic
Dedicated 18 x 18 multipliers
JTAG logic compatible with IEEE 1149.1/1532
Up to 1,872 Kbits of total block RAM
Up to 520 Kbits of total distributed RAM
Clock skew elimination
Frequency synthesis
High resolution phase shifting
Block RAM
(K=1024)
1,728K
1,872K
216K
288K
432K
576K
720K
72K
Bits
®
PIPE
Spartan-3 XA Family
Endpoint, and other
Multipliers
Dedicated
104
Xilinx ISE
12
16
24
32
40
96
4
DCMs
®
2
4
4
4
4
4
4
4
variant
and WebPACK™
up to 333 Mbps
IP cores
Maximum
User I/O
124
173
264
391
487
565
633
633
PCI
Differential
Maximum
I/O Pairs
270
300
300
116
175
221
®
76
56
,
PCI
3