XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 117

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bitstream Options
Table 79
on a Spartan-3 FPGA. The table shows the names of the
affected pins, describes the function of the bitstream option,
Table 79: Bitstream Options Affecting Spartan-3 Pins
DS099-4 (v2.5) December 4, 2009
Product Specification
All unused I/O pins of
type I/O, DUAL,
GCLK, DCI, VREF
IO_Lxxy_#/DIN,
IO_Lxxy_#/DOUT,
IO_Lxxy_#/INIT_B
IO_Lxxy_#/D0,
IO_Lxxy_#/D1,
IO_Lxxy_#/D2,
IO_Lxxy_#/D3,
IO_Lxxy_#/D4,
IO_Lxxy_#/D5,
IO_Lxxy_#/D6,
IO_Lxxy_#/D7,
IO_Lxxy_#/CS_B,
IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY,
IO_Lxxy_#/INIT_B
CCLK
CCLK
PROG_B
DONE
DONE
M2
M1
Affected Pin
Name(s)
lists the various bitstream options that affect pins
R
For all I/O pins that are unused in the application after
configuration, this option defines whether the I/Os are individually
tied to VCCO via a pull-up resistor, tied ground via a pull-down
resistor, or left floating. If left floating, the unused pins should be
connected to a defined logic level, either from a source internal to
the FPGA or external.
Serial configuration mode: If set to Yes, then these pins retain their
functionality after configuration completes, allowing for device
(re-)configuration. Readback is not supported in with serial mode.
Parallel configuration mode (also called SelectMAP): If set to Yes,
then these pins retain their SelectMAP functionality after
configuration completes, allowing for device readback and for
partial or complete (re-)configuration.
After configuration, this bitstream option either pulls CCLK to
VCCAUX via a pull-up resistor, or allows CCLK to float.
For Master configuration modes, this option sets the approximate
frequency, in MHz, for the internal silicon oscillator.
A pull-up resistor to VCCAUX exists on PROG_B during
configuration. After configuration, this bitstream option either
pulls PROG_B to VCCAUX via a pull-up resistor, or allows
PROG_B to float.
After configuration, this bitstream option either pulls DONE to
VCCAUX via a pull-up resistor, or allows DONE to float. See also
DriveDone option.
If set to Yes, this option allows the FPGA’s DONE pin to drive High
when configuration completes. By default, the DONE is an
open-drain output and can only drive Low. Only single FPGAs and
the last FPGA in a multi-FPGA daisy-chain should use this option.
After configuration, this bitstream option either pulls M2 to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows M2 to float.
After configuration, this bitstream option either pulls M1 to
VCCAUX via a pull-up resistor, to ground via a pull-down resistor,
or allows M1 to float.
Bitstream Generation Function
www.xilinx.com
the name of the bitstream generator option variable, and the
legal values for each variable. The default option setting for
each variable is indicated with bold, underlined text.
Spartan-3 FPGA Family: Pinout Descriptions
ConfigRate
UnusedPin
DriveDone
Variable
DonePin
ProgPin
CclkPin
Option
Persist
Persist
M2Pin
M1Pin
Name
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3, 6, 12, 25,
50
(default
Values
Pulldown
Pullup
Pullnone
No
Yes
No
Yes
Pullup
Pullnone
Pullup
Pullnone
Pullup
Pullnone
No
Yes
Pullup
Pulldown
Pullnone
Pullup
Pulldown
Pullnone
value)
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