XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 92

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: DC and Switching Characteristics
Configuration and JTAG Timing
Table 64: Power-On Timing and the Beginning of Configuration
92
Notes:
1.
2.
3.
The numbers in this table are based on the operating conditions set forth in
V
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only for the Master Serial and Master Parallel modes.
CCINT
Symbol
T
T
T
T
ICCK
POR
T
PROG
V
V
V
PROG_B
INIT_B
CCLK
PL
Notes:
1.
2.
3.
INIT
(Supply)
(Supply)
(Supply)
(Input)
(Open-Drain)
(Output)
CCINT
CCAUX
CCO
(2)
, V
(2)
(3)
The V
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
CCO
Bank 4
, and V
CCINT
The time from the application of V
Bank 4 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
, V
Figure 34: Waveforms for Power-On and the Beginning of Configuration
CCAUX
CCAUX
lines.
, and V
CCO
1.0V
2.0V
1.0V
supplies may be applied in any order.
Description
CCINT
T
T
www.xilinx.com
POR
PROG
, V
CCAUX
, and V
T
PL
CCO
Table
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
All
T
31. This means power must be applied to all
ICCK
Device
DS099-3 (v2.5) December 4, 2009
All Speed Grades
0.25
Min
250
0.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS099-3_03_120604
Product Specification
Max
4.0
5
5
5
5
7
7
7
7
2
2
2
2
3
3
3
3
-
-
1.2V
2.5V
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
μs
ns
μs
R