XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 29

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Choosing the READ_FIRST attribute, data already stored in
the addressed location pass to the DO outputs before that
location is overwritten with new data from the DI inputs on
Choosing a third attribute called NO_CHANGE puts the DO
outputs in a latched state when asserting WE. Under this
condition, the DO outputs will retain the data driven just
DS099-2 (v2.5) December 4, 2009
Product Specification
R
Figure 13: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected
Figure 14: Waveforms of Block RAM Data Operations with READ_FIRST Selected
ADDR
ADDR
CLK
CLK
WE
WE
DO
DO
EN
EN
DI
DI
DISABLED
DISABLED
0000
0000
XXXX
XXXX
aa
aa
READ
READ
MEM(aa)
MEM(aa)
www.xilinx.com
1111
bb
MEM(bb)=1111
1111
bb
MEM(bb)=1111
WRITE
WRITE
old MEM(bb)
an enabled active CLK edge. READ_FIRST timing is shown
in the portion of
before WE was asserted. NO_CHANGE timing is shown in
the portion of
1111
Spartan-3 FPGA Family: Functional Description
2222
cc
2222
cc
MEM(cc)=2222
MEM(cc)=2222
WRITE
WRITE
old MEM(cc)
Figure 15
2222
Figure 14
during which WE is High.
dd
dd
DS099-2_14_030403
DS099-2_15_030403
during which WE is High.
XXXX
XXXX
READ
READ
MEM(dd)
MEM(dd)
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