XC3S200-4TQG144I Xilinx Inc, XC3S200-4TQG144I Datasheet - Page 19

• Manufacturer Part Number: XC3S200-4TQG144I
• Description: FPGA Spartan®-3 Family 200K Gates 4320 Cells 630MHz 90nm Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S200-4TQG144I

• Package: 144TQFP
• Family Name: Spartan®-3
• Device Logic Units: 4320
• Device System Gates: 200000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 97
• Ram Bits: 221184
• Package / Case: 144-TQFP, 144-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.14 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 97
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10: DCI Terminations
DS099-2 (v2.5) December 4, 2009
Product Specification
Notes:
1.
2.
3.
Controlled impedance output driver
Controlled output driver with half impedance
Single resistor
Split resistors
Split resistors with output driver impedance
fixed to 25Ω
The value of R is equivalent to the characteristic impedance of the line connected to the I/O. It is also equal to half the value of R
for the DV2 standards and R
For DCI using HSTL Classes I and III, terminations only go into effect at inputs (not at outputs).
For DCI using SSTL Class I, the split termination only goes into effect at inputs (not at outputs).
R
Termination
REF
for all other DCI standards.
IOB
IOB
IOB
IOB
IOB
www.xilinx.com
25Ω
R/2
Schematic
R
V
V
V
CCO
CCO
CCO
Spartan-3 FPGA Family: Functional Description
(1)
R
2R
2R
2R
2R
Z
Z
Z
0
Z
0
Z
0
0
0
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
HSLVDCI_15
HSLVDCI_18
HSLVDCI_25
HSLVDCI_33
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
GTL_DCI
GTLP_DCI
HSTL_III_DCI
HSTL_III_DCI_18
HSTL_I_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
DIFF_HSTL_II_18_DCI
DIFF_SSTL2_II_DCI
LVDS_25_DCI
LVDSEXT_25_DCI
SSTL18_I_DCI
SSTL2_I_DCI
SSTL2_II_DCI
Signal Standards
(IOSTANDARD)
(2)
(3)
(2)
(3)
(2)
(2)
REF
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