AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 101

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Power Management Status and Control
This register is reserved if Dev[B,A]:0x48[HPEN] is low.
Default: 0000 0000h
Chapter 3
Bits
31:24
23
22:16
15
14:9
8
7:2
1:0
Description
Reserved.
Bus Power/Clock Control Enable [BPCC_EN]. Read Only. Indicates the bus power/clock control
policies defined in section 4.7.1 of the PCI Bus Power Management Interface Specification, Rev. 1.1, have
been disabled.
Reserved.
PME_L Status [PME_STS]. Read. Set by hardware. Write 1 to clear. Set when [B,A]_PME_L is
asserted as a result of an SHPC PME event. See SHPC[B,A]:20.
Reserved.
PME Enable [PME_EN]. Read-Write.
0 = Not enabled.
1 = Enables [B,A]_PME_L assertion if Dev[B,A]:0x9C[PME_STS] is set.
Reserved.
Power State [PWRS]. Read-Write. Indicates the current power state of the function. 00b = D0. 11b =
D3 hot. If software attempts to write unsupported state to this field (01b = D1 or 10b = D2), the write
operation completes normally on the bus; however, the data is discarded and no state change occurs.
AMD-8132™ HyperTransport™ PCI-X
Registers
®
Attribute: See Below
2.0 Tunnel Data Sheet
Dev[B,A]:0x9C
101