AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 110

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
Tunnel Control
Default: 0303 000Ch
110
7:0
Bits
31:27
26
25:24
23:19
18
Non-Prefetchable Upper Memory Base [NPUMB]. This field provides bits[39:32] of the non-
prefetchable memory space address base specified by Dev[B,A]:0x20[MEMBASE]. See
Dev[B,A]:0x1C.
Note: NPUML and NPUMB are both device A registers but they affect both device A and device B non-
Description
RxLookahd1. Read-Write. Resets to 0. This field allows software to cause the link 1 receive sync
FIFO to look at data ahead of the FIFO entries that its edge synchronizers currently show as valid.
This value indicates the minimum number of receive clock edges to be received in the time the edge
synchronizer takes to operate, thus hiding some part of the synchronizer latency.
Default = 0 (meaning no lookahead, and is therefore safe)
Note: This bit is cleared by PWROK reset, not by LDTRESET_L. After this field is updated, the new value is not
RxHwLookahdEn1. Read-Write. Resets to 0. Setting this bit enables hardware generation of
lookahead values based on sampled frequency. If this bit is 0, the software-written value in
RxLookahd1 is used. BIOS is expected to set this bit to 1.
Note: This bit is cleared by PWROK reset, not by LDTRESET_L. After this field is updated, the new value is not
TxSlack1. Read-Write. This register adds slack to synchronization time in the link 1 transmit clock
forwarding FIFO in units of 1.5 ns. Slack is added to the minimum time that data must be valid in the
FIFO before it is safe to look at in the Tx domain. This field is expected to be written to 0 by BIOS for
lowest-latency operation.
Default = 4.5 ns (most conservative operation)
Note: This bit is initialized by PWROK reset, not by LDTRESET_L. After this field is updated, the new value is not
RxLookahd0. Read-Write. Resets to 0. This field allows software to cause the link 0 receive sync
FIFO to look at data ahead of the FIFO entries that its edge synchronizers currently show as valid.
This value indicates the minimum number of receive clock edges to be received in the time the edge
synchronizer takes to operate, thus hiding some part of the synchronizer latency.
Default = 0 (meaning no lookahead, and is therefore safe)
Note: This bit is cleared by PWROK reset, not by LDTRESET_L. After this field is updated, the new value is not
RxHwLookahdEn0. Read-Write. Resets to 0. Setting this bit enables hardware generation of
lookahead values based on sampled frequency. If this bit is 0, the software-written value in
RxLookahd0 is used. BIOS is expected to set this bit to 1.
Note: This bit is cleared by PWROK reset, not by LDTRESET_L. After this field is updated, the new value is not
prefetchable memory ranges. It is recommended that these registers are left at 0.
applied to the logic until either LDTRESET_L is asserted or a link disconnect sequence occurs through
LDTSTOP_L.
applied to the logic until either LDTRESET_L is asserted or a link disconnect sequence occurs through
LDTSTOP_L.
applied to the logic until either LDTRESET_L is asserted or a link disconnect sequence occurs through
LDTSTOP_L.
applied to the logic until either LDTRESET_L is asserted or a link disconnect sequence occurs through
LDTSTOP_L.
applied to the logic until either LDTRESET_L is asserted or a link disconnect sequence occurs through
LDTSTOP_L.
®
2.0 Tunnel Data Sheet
Registers
26792 Rev. 3.07 July 2005
Attribute: See Below
DevA:0xDC
Chapter 3