AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 111

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 3
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TxSlack0. Read-Write. This register adds slack to synchronization time in the link 0 transmit clock
forwarding FIFO in units of 1.5 ns. Slack is added to the minimum time that data must be valid in the
FIFO before it is safe to look at in the Tx domain. This field is expected to be written to 0 by BIOS for
lowest-latency operation.
Default = 4.5 ns (most conservative operation)
Note: This bit is cleared by PWROK reset, not by LDTRESET_L. After this field is updated, the new value is not
RxFreq1. Read Only. Contains the link frequency, as determined by the link 1 receiver, for the
transmitter to which it is connected. This field is only valid if DevA:0xC8[INITCPLT] is set. It uses the
same frequency encodings as DevA:0xCC[FREQ0] with the addition that 1h is also a legal encoding
indicating 300 MHz.
RxFreq0. Read Only. Contains the link frequency, as determined by the link 0 receiver, for the
transmitter to which it is connected. This field is only valid if DevA:0xC4[INITCPLT] is set. It uses the
same frequency encodings as DevA:0xCC[FREQ0] with the addition that 1h is also a legal encoding
indicating 300 MHz.
Upstream Response Data Error Disable. Read-Write. Resets to 0. When set, this bit prevents the
tunnel from issuing RdResponse or TgtDone packets to the HyperTransport™ chain containing the
Data Error encoding on the error bits. Instead, packets that would normally be issued with a Data Error
encoding are issued as normal (no error) responses. This bit does not affect packets being forwarded
through the tunnel.
Downstream Post Data Error Disable. Read-Write. Resets to 0. When set, this bit causes the tunnel
to ignore the data error bit in received HyperTransport™ posted request packets. The bit is still
preserved in forwarded packets, but the tunnel treats the packet as if the bit were 0.
Chain Disable. Read-Write. Resets to 0. When set, this bit causes the tunnel to ignore the chain bit in
received HyperTransport™ posted request packets. The bit is still preserved in forwarded packets, but
the tunnel treats the packet as if the bit were 0.
DBLINSRATE. Read-Write.
Posted Weight. Read-Write. Resets to 11b. Arbitration between virtual channels to send packets to
any output port (either HyperTransport™ link or the PCI buses) uses a weighted round-robin scheme:
nonposted requests and responses having unit weight and posted requests weighted more weakly.
The weight used for posted requests is determined by this CSR and is equal to 2^-PW. Setting this
CSR to 0 results in posted requests having equal weight with the other two virtual channels. With the
default value, posted requests have 1/8th the weight of other channels.
Stream Disable 1-to-0. Read-Write.
0 = Begin sending packets without waiting for all data to be received. If data is not available for
1 = Require all data associated with a posted request or response to be received from link 1 before the
Note: The default value is to stream for lower latency. In general, the bits should only get set when the link
• If clear (default), the maximum insertion rate onto a busy HyperTransport™ link for packets
• If set, the maximum insertion rate is double the specification-calculated rate.
originating from the two bridges is computed according to the fairness algorithm given in
HyperTransport™ I/O Link Specification, Rev 2.0.
transmission when needed, NOPs will be inserted on link 0.
packet can be forwarded to link 0.
applied to the logic until either LDTRESET_L is asserted or a link disconnect sequence occurs through
LDTSTOP_L.
bandwidths on each side are mismatched.
AMD-8132™ HyperTransport™ PCI-X
Registers
®
2.0 Tunnel Data Sheet
111