AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 98

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
Misc Error Enables
Default: 0000 0000h
98
Bits
31:17
16
15
14
13
12
11
10
9
8
7
6
5
4
Description
Reserved.
Discarded Post Log Override. When asserted, this bit causes the discarded post log bit
Dev[B,A]:0x80[1] to be set if, due to receiving a master abort or a target abort, the bridge is forced to
discard a posted request it was trying to forward to PCI/PCI-X
Dev[B,A]:0x3C[21] is cleared.
Received Secondary Master Abort Nonfatal Enable. When asserted, this bit causes nonfatal error
interrupt assertion whenever the log bit Dev[B,A]:0x1C[29] is set.
Received Secondary Master Abort Fatal Enable. When asserted, this bit causes fatal error interrupt
assertion whenever the log bit Dev[B,A]:0x1C[29] is set.
Primary Signalled Master Abort Fatal Enable. When asserted, this bit causes fatal error interrupt
assertion whenever the log bit DevA:0x80[19] is set.
Note: This CSR only exists in DevA. This bit is Reserved in DevB.
Primary Signalled Master Abort Nonfatal Enable. When asserted, this bit causes nonfatal error
interrupt assertion whenever the log bit DevA:0x80[19] is set.
Note: This CSR only exists in DevA. This bit is Reserved in DevB.
PCI Busy Time Out Fatal Enable. When asserted, this bit causes fatal error interrupt assertion
whenever the log bit Dev[B,A]:0x80[18] is set.
Depending on how the secondary bus hangs, the AMD-8132 tunnel can be involved in the operation in
such a way that the error log bit will be set but the system software interrupt cannot be issued from the
AMD-8132 tunnel to the HyperTransport™ bus because internal resources are in use as part of the
hung bus operation, thus blocking the interrupt packet.
PCI Busy Time Out Nonfatal Enable. When asserted, this bit causes nonfatal error interrupt
assertion whenever the log bit Dev[B,A]:0x80[18] is set.
Depending on how the secondary bus hangs, the AMD-8132 tunnel can be involved in the operation in
such a way that the error log bit will be set but the system software interrupt cannot be issued from the
AMD-8132 tunnel to the HyperTransport™ bus because internal resources are in use as part of the
hung bus operation, thus blocking the interrupt packet.
Signalled Secondary Target Abort Nonfatal Enable. When asserted, this bit causes nonfatal error
interrupt assertion whenever the log bit Dev[B,A]:0x1C[27] is set.
Signalled Secondary Target Abort Fatal Enable. When asserted, this bit causes fatal error interrupt
assertion whenever the log bit Dev[B,A]:0x1C[27] is set.
Received Secondary Target Abort Nonfatal Enable. When asserted, this bit causes nonfatal error
interrupt assertion whenever the log bit Dev[B,A]:0x1C[28] is set.
Received Secondary Target Abort Fatal Enable. When asserted, this bit causes fatal error interrupt
assertion whenever the log bit Dev[B,A]:0x1C[28] is set.
SCM_Class 1_TargetAbortErrNonfatalEn. When asserted, this bit causes nonfatal error interrupt
assertion whenever the log bit Dev[B,A]:0x80[17] is set.
SCM_Class 1_TargetAbortErrFatalEn. When asserted, this bit causes fatal error interrupt assertion
whenever the log bit Dev[B,A]:0x80[17] is set.
®
2.0 Tunnel Data Sheet
Registers
®
even if the master abort mode bit
26792 Rev. 3.07 July 2005
Attribute: Read-Write
Dev[B,A]:0x84
Chapter 3