AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 22

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
Figure 3. AMD-8132™ Tunnel Interrupt Routing
1.3.2.1
The HyperTransport interrupt discovery and configuration capability block defines the mechanism for
declaring the number of interrupt sources for each bridge and allows software to configure each interrupt
independently. Each bridge has its own capability block to facilitate mapping interrupt sources to
HyperTransport interrupt packets. If existing software cannot use this mapping, then see HyperTransport™I/O
Link Specification, Rev 2.0, Appendix F.1.4 and section 3.6 herein for APIC compatible interrupt
configuration. This alternative method of configuring and mapping interrupts utilizes a standard set of IOAPIC
registers. Each bridge has an associated set of IOAPIC registers that includes a standard PCI function header
(function 1 of each bridge) and memory mapped registers. This mapping provides an alternate way to access a
subset of the interrupt discovery and configuration register set.
Each bridge supports the four PCI-defined interrupt signals, [B,A]_PIRQ[D,C,B,A]_L. Assertion of these
interrupt signals may be converted to link interrupt request messages or cause assertion of the
22
NIOAIRQA
NIOAIRQA
NIOAIRQB
NIOAIRQB
NIOAIRQC
NIOAIRQC
NIOAIRQD
NIOAIRQD
HT Interrupt Packet
HT Interrupt Packet
HT Virtual Wire Packet
HT Virtual Wire Packet
= connection via pad
= connection via pad
A_PIRQ[A-D]_L are open drain
A_PIRQ[A-D]_L are open drain
NIOAIRQ[A-D] are open drain
NIOAIRQ[A-D] are open drain
IM = Interrupt Mask bit in IOAPIC register
IM = Interrupt Mask bit in IOAPIC register
Interrupt Discovery and Configuration
B_NIOAIRQA
B_NIOAIRQA
A_NIOAIRQA
A_NIOAIRQA
B_NIOAIRQB
B_NIOAIRQB
A_NIOAIRQB
A_NIOAIRQB
B_NIOAIRQC
B_NIOAIRQC
A_NIOAIRQC
A_NIOAIRQC
B_NIOAIRQD
B_NIOAIRQD
A_NIOAIRQD
A_NIOAIRQD
®
2.0 Tunnel Data Sheet
Functional Operation
0x40[NIOAMODE]
0x40[NIOAMODE]
IM[16h]
IM[16h]
IM[14h]
IM[14h]
IM[12h]
IM[12h]
IM[10h]
IM[10h]
IM[10h]
IM[10h]
IM[12h]
IM[12h]
IM[14h]
IM[14h]
IM[16h]
IM[16h]
0x48[INTx_PACKET_EN]
0x48[INTx_PACKET_EN]
IM[10h]
IM[10h]
IM[12h]
IM[12h]
IM[14h]
IM[14h]
IM[16h]
IM[16h]
26792 Rev. 3.07 July 2005
Chapter 1
{0xFC[UPPE
{0xFC[UPPE
= PCI Addr
= PCI Addr
0xF4[MSI_
0xF4[MSI_
A_PIRQA_
A_PIRQA_
A_PIRQB_
A_PIRQB_
A_PIRQC_
A_PIRQC_
A_PIRQD_
A_PIRQD_
IM[1Ch]
IM[1Ch]
SHPC
SHPC
IM[18h]
IM[18h]
fatalErr
fatalErr
IM[1Ah]
IM[1Ah]
nonFatalE
nonFatalE
0xF8[LOW
0xF8[LOW
PCI B
PCI B