AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 26

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
In general, the PCI specification indicates that MRLs and MRMs are always prefetchable; it is the
responsibility of masters to issue them only to prefetchable targets. No such assumption can be made for MRs.
If, by means outside the PCI specification, it is known that MRs issued by the devices on this bus are to
prefetchable targets, then the Dev[B,A]:0x4C[MRPFEN] bit can be set to enable prefetching for MRs. In this
case, the MRL prefetching controls are used to control MR prefetching as well.
When prefetching is disabled for a memory read request (either Dev[B,A]:0x40[PFEN_L] deasserted for the
particular master, or the request is an MR with Dev[B,A]:0x4C[MRPFEN] deasserted), these rules are
followed:
When prefetching is enabled for a memory read request (Dev[B,A]:0x40[PFEN_L] asserted for the particular
master and Dev[B,A]:0x4C[MRPFEN] asserted if the request is an MR), these rules are followed:
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• Burst Request: a cycle in which FRAME_L is held asserted during the first clock in which IRDY_L is
• Acquired Line: all or part of a requested line of data within a 64-byte aligned block that has made it back to
• Requested Prefetch: the prefetch of up to a line of data in which the master has explicitly requested the line
• Unrequested Prefetch: the speculative prefetch of a full line before a master has generated a transaction
• The AMD-8132 tunnel generates no unrequested prefetches.
• MRs with prefetching off are one DW, regardless of REQ64_L, and never assert ACK64_L.
• If REQ64_L is asserted, MRLs and MRMs with prefetching off assert ACK64_L and fetch two DW from
• The AMD-8132 tunnel may contain between 0 and 8 cache lines of prefetched data for a memory read at
• If not bursted, all types of memory reads assert ACK64_L if REQ64_L is asserted and fetch two DW from
• When there is a memory burst request, then the AMD-8132 tunnel sends out a requested prefetch of data
• As soon as the AMD-8132 tunnel completes transferring data for a given line, it may send another
asserted, indicating the master wishes to transfer more than one beat of data. In the event that STOP_L is
asserted before IRDY_L asserts, FRAME_L always deasserts as IRDY_L asserts (PCI Local Bus
Specification, Rev 2.3, section 3.3.3.2.1). In such case, the master's intention to burst cannot be determined
and the AMD-8132 tunnel pessimistically treats such cycles as burst requests.
the AMD-8132 tunnel from the HyperTransport interface.
by initiating a transaction in which the address is within the prefetched line.
that includes the address of the line. If a master bursts up to the end of a requested prefetched line while
keeping FRAME_L asserted and the AMD-8132 tunnel disconnects with data at that point, then the next
line is still considered an unrequested prefetch even though the master has attempted to burst into the next
line. Even if a burst is sustained from a requested line through any or all of an unrequested line, the second
line is not considered requested by the master. If after a disconnect before or during data phases of an
unrequested line the master subsequently attempts to continue the burst and generates an address phase that
resides within the unrequested line, then that line changes from an unrequested prefetch to a requested
prefetch.
HyperTransport. If REQ64_L is deasserted, only one DW is fetched.
one time.
HyperTransport. If REQ64_L is deasserted, only one DW is fetched.
starting from the transaction address up to the end of the line. Additionally, the AMD-8132 tunnel may
send out 0 to 7 unrequested prefetches as controlled by Dev[B,A]:0x4C[IPF_x] where x is either an MRL
or MRM. Prefetch-enabled MRs use IPF_MRL.
unrequested prefetch as controlled by Dev[B,A]:0x4C[CPFEN_x] where x could be an MRL or MRM.
Prefetch-enabled MRs use CPF_MRL.
®
2.0 Tunnel Data Sheet
Functional Operation
26792 Rev. 3.07 July 2005
Chapter 1