AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 150

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
5.1.4
HyperTransport receive buffer overflow errors are defined in HyperTransport™ I/O Link Specification, Rev
2.0, section 10.1.4. The error is logged by setting the appropriate DevA:0x[CC,D0][13] Overflow Error bit.
The overflow error bits can be enabled to trigger sync flooding by setting DevA:0xD4[17]. The overflow error
bits can also be enabled to trigger fatal or nonfatal interrupt assertion by setting DevA:0xD4[19] or
DevA:0xD4[27] respectively. All overflow errors cause the receiver to lock up and process no more incoming
packets from that link if sync flooding is enabled.
5.1.5
End of Chain (EOC) receive buffer overflow errors are defined in HyperTransport™ I/O Link Specification,
Rev 2.0, section 10.1.5. If the AMD-8132 tunnel receives a packet from a HyperTransport link that the routing
rules indicate is to be forwarded to the far link, but the far transmitter is unable to transmit it, the packet is
handled as an end of chain packet and dropped. Reasons for the transmitter to drop a packet are:
All other transmitter conditions that prevent transmission are assumed to be temporary and cause the packets to
remain queued for transmission, rather than being dropped.
Other actions taken depend on the type of packet that was dropped:
5.1.6
The AMD-8132 tunnel does not support atomic read-modify requests as a target. If an atomic read-modify
request is received that targets one of the PCI/PCI-X bridges, the request is dropped and a target abort response
returned from that bridge. Read-modify-writes that do not target the AMD-8132 bridges are forwarded through
the tunnel normally.
5.1.7
The AMD-8132 tunnel only supports HyperTransport nonposted reads and writes to its configuration and I/O
spaces. These nonposted reads and writes must fall within a 32-bit-aligned block. Posted accesses to
configuration or I/O spaces owned by the AMD-8132 tunnel result in undefined behavior. Nonposted reads or
writes of greater than 1 DW, or atomic read-modify writes, result in the request being dropped and returning a
target abort response. Accesses of greater than 1 DW to memory-mapped registers through AMD-8132 tunnel
BARs (APIC or SHPC) result in undefined behavior.
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• The DevA:0x[C4,C8][6] ENDOCH bit for that transmitter is set.
• The DevA:0x[C4,C8][5] INITCPLT bit for that transmitter is clear and DevA:0xC0[28] DOUI is set.
• The packet is a request with an extended address and DevA:0x[C4,C8][15] 64BEn for that transmitter is
• Broadcasts, and DIMs with the Silent Drop bit set, are dropped silently. No other action is taken.
• All other posted requests and responses cause the DevA:0x[CC,D0][14] End Of Chain Error bit associated
• Nonposted requests cause the appropriate type of response packet to be generated, with a master abort
clear.
with the transmitter to be set. The EOC error bits can be enabled to trigger fatal or nonfatal interrupt
assertion by setting DevA:0xD4[20] or DevA:0xD4[28] respectively.
error status.
Receive Buffer Overflow Errors
End of Chain (EOC) Errors
Atomic Read-Modify-Write Requests
Illegal Configuration and I/O Accesses
Error Conditions and Handling
®
2.0 Tunnel Data Sheet
26792 Rev. 3.07 July 2005
Chapter 5