AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 73

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
PCI-X
Default: 0000 0000h
PCI-X
Default: ?000 0000h
PCI-X
Secondary Status
These registers specify the address windows for I/O space Dev[B,A]:0x1C and Dev[B,A]:0x3; non-
prefetchable memory space Dev[B,A]:0x20; and prefetchable memory space Dev[B,A]:0x24, Dev[B,A]:0x28,
and Dev[B,A]:0x2C. These address windows are for transactions mapped from the HyperTransport link
address space to the secondary PCI bus.
Chapter 3
Bits
31:0
Bits
31:27
26:24
23:16
15:8
7:0
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®
®
Description
SHPC Base Address Register [SHPCBAR] High. These bits specify bits [63:32] of the memory
address space of the SHPC register set SHPC[B,A]:XX. If Dev[B,A]:0x48[HPEN] is low, the
SHPCBAR is forced to read only 0.
Description
Secondary Latency Timer [SECLAT[7:3]]. Read-Write. The default value of SECLAT[7:0] after the
deassertion of LDTRESET_L is 00h when the bridge is in conventional PCI mode and 40h when the
bridge is in PCI-X
Note: This register is not reset on a secondary ([B,A]_RESET_L) reset assertion. If the bus mode is changed
Secondary Latency Timer [SECLAT[2:0]]. Read Only (000b).
Subordinate PCI Bus Number [SUBBUS]. Read-Write.
Secondary PCI Bus Number [SECBUS]. Read-Write.
Primary PCI Bus Number [PRIBUS]. Read-Write.
SHPC Base Address High
Bridge Bus Numbers and Secondary Latency
Bridge Memory Base/Limit, I/O Base/Limit, and
• In conventional PCI mode, this functions per the PCI Local Bus Specification, Rev 2.3.
• In PCI-X mode, the latency timer is not used when the AMD-8132 tunnel is the master of host-
initiated transactions to the PCI-X bus. In PCI-X mode, the latency timer limits the number of
clocks that the AMD-8132 tunnel owns the bus as the completer (master) only during split
completions. For these transactions, the latency timer counts while [B,A]_FRAME_L is asserted. If
the latency timer exceeds SECLAT and the arbiter has deasserted the grant signal for the
AMD-8132 tunnel because another master is requesting the bus, then the transaction is
disconnected by the AMD-8132 tunnel at the next convenient 128-byte boundary.
between PCI and PCI-X through a secondary reset event, it is the responsibility of software to set SECLAT
for the new mode.
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mode.
AMD-8132™ HyperTransport™ PCI-X
Registers
Dev[B,A]:0x[30:1C]
®
Attribute: Read-Write
Attribute: See Below
2.0 Tunnel Data Sheet
Dev[B,A]:0x14
Dev[B,A]:0x18
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