AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 149

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 5
In general, for errors detected by the AMD-8132™ HyperTransport™ PCI-X
condition sets one or more log bits that are persistent through warm reset and cleared by writing ones to them.
The log bits are readable from software and may also be mapped to the various reporting methods listed in this
chapter.
5.1
5.1.1
Once its link receivers are initialized, if the AMD-8132 tunnel detects sync flooding in either link receiver, it
propagates sync flooding out its active transmitters. No enables are required. No logging is performed.
5.1.2
HyperTransport CRC Errors are defined in HyperTransport™ I/O Link Specification, Rev 2.0, sections 10.1.1
and 10.1.2. When a CRC error is detected, logging of the error is delayed until L[1:0]_CTLIN for the
associated link asserts. If LDT_RESET_L asserts before L[1:0]_CTLIN, the error status is lost. The error is
logged by setting the appropriate DevA:0x[C4,C8][9:8] CRCERR bit, based on which link and byte lane
detected the error.
The CRCERR bits for each link can be enabled to trigger sync flooding by setting the appropriate
DevA:0x[C4,C8][1] CRCFEN bit. The CRCERR bits for both links can be enabled to trigger fatal or nonfatal
interrupt assertion by setting the enables located at DevA:0xD4[22] or DevA:0xD4[30], respectively.
5.1.3
HyperTransport protocol errors are defined in HyperTransport™ I/O Link Specification, Rev 2.0, section
10.1.3. In addition to all the conditions listed in the released HyperTransport specification, the
AMD-8132 tunnel also detects orphan address extension protocol errors, as defined in
HyperTransport™ I/O Link Errata, Rev 1.05c.
As required by HyperTransport™ I/O Link Specification, Rev 2.0, logging of all protocol errors other than
CTL timeout is delayed until L[1:0]_CTLIN for the associated link asserts. If LDT_RESET_L asserts before
L[1:0]_CTLIN, the error status is lost. Expiration of the CTL timer results in immediate logging of a protocol
error. The error is logged by setting the appropriate DevA:0x[CC,D0][12] Protocol Error bit. The duration of
CTL timer is controlled by DevA:0x[CC,D0][15].
The protocol error bits can be enabled to trigger sync flooding by setting DevA:0xD4[16]. The protocol error
bits can be enabled to trigger fatal or nonfatal interrupt assertion by setting DevA:0xD4[18] or DevA:0xD4[26]
respectively.
With the exception of CTL deassertion during CRC, all protocol errors cause the receiver to lock up and
process no more incoming packets from that link if sync flooding is enabled.
Chapter 5
HyperTransport™ Interface Errors
Sync Flood
CRC Errors
Protocol Errors
Error Conditions and Handling
Error Conditions and Handling
AMD-8132™ HyperTransport™ PCI-X
®
2.0 tunnel each detectable error
®
2.0 Tunnel Data Sheet
149