AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 131

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
3.6
These registers are located in APIC[B,A]:XX memory space. The base address register for these registers is
found at Dev[B,A]:1x48, and Dev[B,A]:1x10 if enabled.
The IOAPIC register set supports 7 interrupts and corresponding redirection registers. The space is indexed
through two memory-mapped ports:
Accesses that span multiple 32-bit blocks result in undefined behavior. Writes to APIC[B,A]:10h (the 32-bit
data port) must be 32-bit aligned accesses, other than 32-bit writes result in undefined behavior. Reads provide
all four bytes regardless of the byte enables.
Only bits 7:0 of APIC[B,A]:00 are used. The index written to APIC[B,A]:00 selects one from the following
table.
Chapter 3
0
• See section 3.1.2 for a description of the register naming convention.
• See section 1.3.2 for more details about interrupt operation.
• See Dev[B,A]:0x[BC,B8] for a description of alternative access to these registers and expanded
• See 82093AA I/O Advanced Programmable Interrupt Controller (IOAPIC) Product Data for more
• APIC[B,A]:00h (offset 00h of the address space indicated by Dev[B,A]:1x10/Dev[B,A]:1x48) provides the
• APIC[B,A]:10h (offset 10h of the address space indicated by Dev[B,A]:1x10/Dev[B,A]:1x48) provides the
8-bit index register.
32-bit data port. All accesses (reads or writes) to APIC registers must fit within a 32-bit aligned block.
programmability.
information.
Counter Enable. Enables/disables for this bit differ for Control0 and Control1 as follows:
Default = 0
Control1[0]
0
0
1
1
IOAPIC Register Space
Control0[0]
0
1
0
1
AMD-8132™ HyperTransport™ PCI-X
Registers
Counter1
Disabled
Disabled
Disabled
Enabled
Counter0
Disabled
Enabled
Disabled
Enabled
®
2.0 Tunnel Data Sheet
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