AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 68

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
Table 6.
68
Register Name
PCI-X
PCI-X Bridge Status and Command
PCI-X Bridge Revision and Class Code
PCI-X Bridge BIST-Header-Latency-Cache
PCI-X SHPC Base Address Low
PCI-X SHPC Base Address High
PCI-X Bridge Bus Numbers and Secondary Latency
PCI-X Bridge Memory Base/Limit, I/O Base/Limit, and Secondary Status Dev[B,A]:0x[30:1C]
PCI-X Bridge Capabilities Pointer
PCI-X Bridge Interrupt and Bridge Control
PCI-X Miscellaneous
PCI-X Scratch
PCI-X Misc II and Pins Latched at Rising Edge of PWROK
Prefetch Control
PCI-X Secondary Status
PCI-X Bridge Status
PCI-X Upstream Split Transaction
PCI-X Downstream Split Transaction
PCI-X ECC Control and Status
PCI-X ECC First Address
PCI-X ECC Second Address
PCI-X ECC Attribute
Misc Bridge Errors
Misc Error Enables
SHPC Capabilities
SHPC Data
Power Management Capabilities
Power Management Status and Control
Extended Configuration Address Range
Interrupt Discovery and Configuration
HyperTransport™ Revision ID Capability Block
Link Command
Link Configuration and Control
®
Bridge Vendor and Device ID
AMD-8132™ Tunnel Registers and Register Addresses
®
2.0 Tunnel Data Sheet
Registers
Register Address
Dev[B,A]:0x00
Dev[B,A]:0x04
Dev[B,A]:0x08
Dev[B,A]:0x0C
Dev[B,A]:0x10
Dev[B,A]:0x14
Dev[B,A]:0x18
Dev[B,A]:0x34
Dev[B,A]:0x3C
Dev[B,A]:0x40
Dev[B,A]:0x44
Dev[B,A]:0x48
Dev[B,A]:0x4C
Dev[B,A]:0x60
Dev[B,A]:0x64
Dev[B,A]:0x68
Dev[B,A]:0x6C
Dev[B,A]:0x70
Dev[B,A]:0x74
Dev[B,A]:0x78
Dev[B,A]:0x7C
Dev[B,A]:0x80
Dev[B,A]:0x84
Dev[B,A]:0x90
Dev[B,A]:0x94
Dev[B,A]:0x98
Dev[B,A]:0x9C
DevA:0xB4
Dev[B,A]:0x[BC,B8]
DevB:0xC0
DevA:0xC0
DevA:0xC4 and DevA:0xC8
26792 Rev. 3.07 July 2005
Chapter 3