AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 156

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
Uncorrectable Error Response Enable (PEREN) in the Bridge Control CSR can be mapped to cause sync
flooding by clearing Dev[B,A]:0x40[21] PciErrorSerrDisable, or to fatal/nonfatal interrupt assertion by setting
Dev[B,A]:0x40[22,23] PciErrorFatalEn/PciErrorNonFatalEn.
5.2.5
PCI/PCI-X End of Chain errors occur when a request is received from the PCI/PCI-X bus, and the
AMD-8132 tunnel address decode and routing controls are configured to accept that request and send it to a
transmitter that is unable to take it, as described in section 5.1.5. In that case, the AMD-8132 tunnel does not
assert [B,A]_DEVSEL_L, allowing the request to master abort on the PCI/PCI-X bus. No log bits are set.
5.2.6
When the secondary bus is in PCI mode, all inbound nonposted requests are handled as delayed requests. Each
delayed request has a discard timer associated with it which starts running when the AMD-8132 tunnel has
received a response from HyperTransport and is ready to return it to the PCI bus. The discard timer runs for
either 1K or 32K PCI clock cycles, depending on the value of the Dev[B,A]:0x3C[25] Secondary Discard
Timer (SDT) bit in the Bridge Control CSR. If the PCI master does not retry the transaction within that time,
the contents of the delayed request buffer are flushed, and the Dev[B,A]:0x3C[26] Discard Timer Status [DTS]
bit in the Bridge Control CSR is set.
DTS can be mapped to cause sync flooding if the Dev[B,A]:0x3C[27] Discard Timer Sync Flood Enable
(DTSE) bit of the Bridge Control CSR is set, and Dev[B,A]:0x40[21] PciErrorSerrDisable is clear. DTS can be
mapped to fatal/nonfatal interrupt assertion if DTSE is set, by setting PciErrorFatalEn/PciErrorNonFatalEn
(Dev[B,A]:0x40[22,23]).
5.2.7
If a master abort is received for a command issued onto the PCI/PCI-X bus by the AMD-8132 tunnel, the
action taken depends on what the command was.
If the command was a posted request, the Dev[B,A]:0x1C[29] Received Master Abort (RMA) bit in the
Secondary Status CSR is set. If Dev[B,A]:0x3C[21] Master Abort Response (MARSP) is set or if
Dev[B,A]:0x84[16] Discarded Post Log Override is set, the AMD-8132 tunnel also sets the Dev[B,A]:0x80[1]
DISCARDED_POST bit in the Misc Bridge Errors CSR. If the Dev[B,A]:0x48[15] CLEARPCILOG_L bit is
set, DISCARDED_POST only pulses high for a single cycle, rather than remaining high.
If the command was either a read or write nonposted request, RMA is set. The response generated back to the
HyperTransport chain depends on MARSP. If MARSP is 0, a normal response is generated with all 1s data for
reads. If MARSP is 1, a target abort response is generated. The Dev[B,A]:0x1C[29] Received Master Abort bit
is set:
If the command was a PCI-X split completion, the AMD-8132 tunnel sets the Dev[B,A]:0x60[18] Split
Completion Discarded (SCD) bit in the PCI-X Secondary Status CSR. DISCARDED_POST and SCD can both
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• If Dev[B,A]:0x84[14] Received Secondary Master Abort Fatal Enable is set, a fatal interrupt is asserted.
• If Dev[B,A]:0x84[15] Received Secondary Master Abort Nonfatal Enable is set, a nonfatal interrupt is
asserted.
End of Chain Errors
PCI Discard Timeouts
Master Aborts
Error Conditions and Handling
®
2.0 Tunnel Data Sheet
26792 Rev. 3.07 July 2005
Chapter 5