AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 69

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Table 6.
Chapter 3
Register Name
Link Revision, Errors, and Frequency Capability 0
Feature, Link Errors, and Frequency Capability 1
Error Handling and Link Enumeration
Link Non-Prefetchable Memory Space Extension
Tunnel Control
Clock Control
MSI Mapping Capability Block Header
MSI Mapping Capability Block Lower Address
MSI Mapping Capability Block Upper Address
IOAPIC Vendor and Device ID
IOAPIC Status and Command
IOAPIC Revision and Class Code
IOAPIC Device BIST-Header-Latency-Cache
IOAPIC Base Address Low
IOAPIC Base Address High
IOAPIC Device Subsystem ID and Subsystem Vendor ID
Pointer to Capabilities Block
IOAPIC Control
HyperTransport Revision Capabilities Block
PCI-X PHY Compensation Control
Link PHY Compensation Control
Performance Counters and Control
IOAPIC Register Space
SHPC Base Offset
SHPC Slots Available I
SHPC Slots Available II
SHPC Slot Configuration
SHPC Secondary Bus Configuration
SHPC Command and Status
SHPC Interrupt Locator
SHPC SERR Locator
SHPC SERR-INT
SHPC Logical Slot
AMD-8132™ Tunnel Registers and Register Addresses (Continued)
AMD-8132™ HyperTransport™ PCI-X
Registers
Register Address
DevA:0xCC
DevA:0xD0
DevA:0xD4
DevA:0xD8
DevA:0xDC
DevA:0xF0
Dev[B,A]:0xF4
Dev[B,A]:0xF8
Dev[B,A]:0xFC
Dev[B,A]:1x00
Dev[B,A]:1x04
Dev[B,A]:1x08
Dev[B,A]:1x0C
Dev[B,A]:1x10 and Dev[B,A]:1x48
Dev[B,A]:1x14 and Dev[B,A]:1x4C
Dev[B,A]:1x2C
Dev[B,A]:1x34
Dev[B,A]:1x44
Dev[B,A]:1x50
Dev[B,A]:1x[94,90,8C,88,84,80]
Dev[B,A]:1x[D8,D4,C8,C4,C0]
DevA:1x[AC,A8,A4,A0]
APIC[B,A]:00[7:0]
SHPC[B,A]:00
SHPC[B,A]:04
SHPC[B,A]:08
SHPC[B,A]:0C
SHPC[B,A]:10
SHPC[B,A]:14
SHPC[B,A]:18
SHPC[B,A]:1C
SHPC[B,A]:20
SHPC[B,A]:[30,2C,28,24]
®
2.0 Tunnel Data Sheet
69