AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 105

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Link Configuration and Control
DevA:0xC4 applies to side 0 of the tunnel and DevA:0xC8 applies to side 1 of the tunnel. The default value for
bit 5 may vary, see the Descriptions.
Default: ??11 0020h
Chapter 3
Bits
31
30:28
27
26:24
23
22:20
19
18:16
15
14
Description
Reserved.
Link Width Out [LWO]. Read-Write. Specifies the operating width of the outgoing link. Legal values
are:
001b (16 bits)
000b (8 bits)
101b (4 bits)
100b (2 bits)
111b (not connected).
Note: This field is cleared by PWROK reset but not by LDTRESET_L. The default value of this field depends on
Reserved.
Link Width In [LWI]. Read-Write. Specifies the operating width of the incoming link. Legal values are:
001b (16 bits)
000b (8 bits)
101b (4 bits)
100b (2 bits)
111b (not connected)
Note: This field is cleared by PWROK reset but not by LDTRESET_L. The default value of this field depends on
Reserved.
Max Link Width Out. Read Only. Specifies the maximum width of the outgoing link to 16 bits.
Reserved.
Max Link Width In. Read Only. Specifies the maximum width of the incoming link to 16 bits.
64-Bit Address Enable [64BEn]. Read-Write.
Extended Control Time During Initialization [EXTCTL]. Read-Write. Specifies the time that
L[1,0]_CTLOUT_[H,L]0 is held asserted during the initialization sequence that follows an LDTSTOP_L
deassertion after L[1,0]_CTLIN_[H,L]0 is detected asserted.
0 = At least 16 bit times.
1 = About 50 microseconds.
Note: This bit is cleared by PWROK reset but not by LDTRESET_L. See section 4.2.1.2.
the widths of the links of the connecting device, per the link specification. After this field is updated, the link
width does not change until either LDTRESET_L is asserted or a link disconnect sequence occurs through
an LDTSTOP_L assertion.
the widths of the links of the connecting device, per the link specification. After this field is updated, the link
width does not change until either LDTRESET_L is asserted or a link disconnect sequence occurs through
an LDTSTOP_L assertion.
AMD-8132™ HyperTransport™ PCI-X
Registers
DevA:0xC4 and DevA:0xC8
®
Attribute: See Below
2.0 Tunnel Data Sheet
105