AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 81

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 3
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PFEN[4:0]_L. Read-Write. Prefetch Enables (active low). Each of these bits apply to the master
attached to one [B,A]_REQ_L/GNT_L pair, Dev[B,A]:0x40[PFEN0_L] applies to
[B,A]_REQ0_L/GNT_L[0] and so forth. In external arbiter mode, PFEN[0]_L applies to all external
masters.
0 = Prefetching is enabled for the specified external master in conventional PCI mode, as controlled
1 = Prefetching is not enabled. All types of memory reads from the given master result in requests
Reserved. Must be set to 1 by BIOS.
Reserved.
Reserved.
Non-Zero Sequence ID [NZSEQID]. Read-Write.
0 = The SeqID value is 0h in the upstream link requests resulting from the bridge's external
1 = The SeqID value is not 0h in the upstream link requests resulting from the bridge's external PCI/
Note:
by the fields in the prefetch control register Dev[B,A]:0x4C.
being issued to the HyperTransport™ chain for the initial PCI beat only, and are completed as non-
burst accesses on PCI. This field is ignored when the bridge is in PCI-X
Dev[B,A]:0x60[SCF] is not zero. It is expected that these bits are normally left at 0. See section
1.3.4.
PCI/PCI-X
PCI-X master read sequences. Instead, a unique SeqID is assigned in the range 8h-Fh for each
read sequence outstanding on the PCI/PCI-X bus. Setting these bits high may reduce host
memory efficiency and bandwidth. It is not expected that these bits will need to be set; the order in
which read requests are delivered to destinations does not matter in most cases. For details see
the SeqId definition in HyperTransport™ I/O Link Specification, Rev 2.0
Reserved.
®
master read sequences.
AMD-8132™ HyperTransport™ PCI-X
Registers
.
®
mode,
®
2.0 Tunnel Data Sheet
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