AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 154

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
5.2.3.2
If [B,A]_PERR_L is asserted on nonposted write data from the AMD-8132 tunnel, it sets the
Dev[B,A]:0x1C[24] Master Data Uncorrectable Error (MDPE) bit in the Secondary Status CSR if the
Dev[B,A]:0x3C[16] Uncorrectable Error Response Enable (PEREN) bit in the Bridge Control CSR is set.
When the TgtDone response is returned to HyperTransport, the AMD-8132 tunnel marks it as a data error
response if the Dev[B,A]:0x04[6] Parity Error Response (PERSP) bit in the appropriate PCI-X Bridge Status
and Command CSR is set, and the global DevA:0xDC[7] Upstream Response Data Error Disable bit is clear.
5.2.3.3
No additional action is taken if [B,A]_PERR_L is asserted on immediate read or split completion data from the
AMD-8132 tunnel.
5.2.4
Depending on bus mode, the AMD-8132 tunnel checks either parity or ECC on all address and attribute phases
on the PCI/PCI-X bus and on all data for which it is the target.
In ECC modes, single-bit ECC errors are considered correctable if the secondary Dev[B,A]:0x70[30] Disable
Single-Bit-Error Correction bit in the PCI-X ECC Error Control and Status CSR is clear. When a correctable
error is detected, correction is performed and the secondary Dev[B,A]:0x70[7] ECC Error Corrected bit is set.
The transaction then proceeds normally.
In parity modes, all parity errors are considered uncorrectable. In ECC modes, multi-bit ECC errors are
uncorrectable, as are single bit errors if the disable single-bit-error correction bit is set. Detection of
uncorrectable errors causes the Dev[B,A]:0x1C[31] Detected Uncorrectable Error (DPE) bit in the Bridge
Control CSR to be set. Other actions are taken depending on the type of transaction and location of the error, as
listed in the following uncorrectable error subsections.
In ECC modes, all correctable or uncorrectable ECC errors cause the following registers to be updated:
Dev[B,A]:0x70[27:8,6:2] PCI-X ECC Control and Status, Dev[B,A]:0x[74,78] PCI-X ECC Addresses, and
Dev[B,A]:0x7C PCI-X ECC Attribute.
5.2.4.1
If the AMD-8132 tunnel detects an uncorrectable error in the address or attribute phase of a PCI/PCI-X
transaction, it sets the Dev[B,A]:0x80[3] ADDR_OR_ATTR_ERROR bit in the Misc. Bridge Errors CSR.
Address decode is not affected by the error. The AMD-8132 tunnel asserts [B,A]_DEVSEL_L normally based
on the address it received. However, it does not propagate the transaction to the HyperTransport chain; rather,
it drops it and issues a target abort on the PCI/PCI-X bus.
If the Dev[B,A]:0x48[15] CLEARPCILOG_L bit is set, ADDR_OR_ATTR_ERROR only pulses high for a
single cycle, rather than remaining high. The combination of ADDR_OR_ATTR_ERROR and
Dev[B,A]:0x3C[16] Uncorrectable Error Response Enable (PEREN) in the Bridge Control CSR can be
mapped to cause sync flooding by clearing Dev[B,A]:0x40[21] PciErrorSerrDisable, or to fatal/nonfatal
interrupt assertion by setting Dev[B,A]:0x40[22,23] PciErrorFatalEn/PciErrorNonFatalEn.
154
PERR_L Assertion on Nonposted Write Data
PERR_L Assertion on Read or Split Completion Data
Parity/ECC Errors
Address/Attribute Phase Uncorrectable Errors
Error Conditions and Handling
®
2.0 Tunnel Data Sheet
26792 Rev. 3.07 July 2005
Chapter 5