AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 24

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
interrupt request message may or may not be sent before the disconnect sequence completes. If it is not sent
before the disconnect sequence completes, then it is not dropped; it is sent after the link is re-connected.
External devices are required to assert PIRQ[D:A]_L for at least 3 PCLK cycles in order to guarantee that the
AMD-8132 tunnel detects the assertion, regardless of the state of the corresponding RDR[TM] field.
1.3.2.2
In addition to the four PCI interrupt pins on each PCI bus, each bridge contains three internal signals that can
generate interrupts. These are the SHPC_INTR signal and the fatal and nonfatal error signals. For each of these
three signals there is an Interrupt Definition register/IOAPIC entry, yielding a total of seven for each bridge.
See section 3.7 for more about SHPC_INTR. See Chapter 5 for more about error reporting.
1.3.2.3
The AMD-8132 tunnel responds to MSIs (as specified in PCI Local Bus Specification, Rev 2.3, section 6.8)
and MSI-Xs (as specified in PCI Local Bus Specification, Rev 3.0, section 6.8) with the following restriction
imposed by HyperTransport:
MSI/MSI-X transactions result in a HyperTransport interrupt packet. The address and data from the MSI/MSI-
X transaction are distributed across that packet according to Table 1.
Table 1.
For more information see PCI Local Bus Specification, Rev 2.3, section 6.8.
24
MSI/MSI-X Field
Address[2], Data[15,10:8]
Address[19:12]
Data[7:0]
Address[11:4]
Address[30:20]
Address[3]
Data[14:11]
Notes:
1. Data[15]/IntrInfo[5] (x86 RQEOI) must be set to 0 by software in PCI and PCI-X devices
2. Data[10:8]/IntrInfo[4:2] (x86 Message Type) can be either 000b for fixed destination delivery
3. IntrInfo[7] (x86MT[3]) is 0b.
4. IntrInfo[31:24] is F8h.
MSI/MSI-X transactions are treated as such only if Dev[B,A]:0xF4[MSI_ENABLE] is set and if bits
[63:20] of the address match the address created by concatenating Dev[B,A]:0xFC[UPPER_ADDRESS]
with Dev[B,A]:0xF8[LOWER_ADDRESS]. Otherwise, they are treated as posted memory writes.
because they do not receive HyperTransport EOI (End of Interrupt) broadcasts.
or 001b for lowest priority delivery.
SHPC_INTR and Fatal/Nonfatal Interrupts
Message Signalled Interrupts (MSI/MSI-X)
MSI/MSI-X Mapping: PCI to HyperTransport™
HyperTransport™ Interrupt Field
IntrInfo[6:2] (x86 DM, RQEOI, MT[2:0])
IntrInfo[15:8] (x86 Destination[7:0])
IntrInfo[23:16] (x86 Vector)
IntrInfo[39:32] (x86 Destination[15:8])
IntrInfo[50:40] (x86 Destination[26:16])
IntrInfo[51] (x86 Destination[27])
IntrInfo[55:52] (x86 Destination[31:28])
®
2.0 Tunnel Data Sheet
Functional Operation
26792 Rev. 3.07 July 2005
Chapter 1