AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 92

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
PCI-X
This register displays primary interface information if the Select Secondary ECC Registers bit is cleared, and
secondary interface information if the Select Secondary ECC Registers bit is set. Since the primary interface is
not PCI-X, it will never receive an ECC error and these registers return 0s if the Select Secondary ECC Regis-
ters bit is cleared. See bit 0 in this register.
Default: ?000 0000h
92
Bits
31
30
29
28
27:24
23:20
19:16
®
Description
ECC Mode. PCI-X
Unless the ECC Control Update Enable bit = 1 in the data pattern being written, writes to this register
do not affect this bit.
In PCI-X Mode 2 this bit is always 1. In Conventional PCI mode, this bit is always 0.
Disable Single-Bit-Error Correction. Read-Write.
Writes to this register do not affect this bit unless the ECC Control Update Enable bit is a 1 in the data
pattern being written.
Default = 0
Reserved.
ECC Control Update Enable. Write. This bit always reads as a 0.
Error Upper Attributes. Read Only. If the ECC Error Phase register is non-zero, this register
indicates the contents of the C/BE_L[3:0] bus for the attribute phase of the transaction that included
the error.
Note: This register is cleared by PWROK, not by LDTRESET_L.
Error Second Command. Read Only. If the ECC Error Phase register is non-zero and the transaction
that included the error used a dual address cycle, this register indicates the contents of the
C/BE[3:0]_L bus for the second address phase of the transaction that included the error.
Note: This register is cleared by PWROK, not by LDTRESET_L.
Error First (or only) Command. Read Only. If the ECC Error Phase register is non-zero, this register
indicates the contents of the C/BE_L[3:0] bus for the first (or only) address phase of the transaction
that included the error.
Note: This register is cleared by PWROK, not by LDTRESET_L.
ECC Control and Status
• If this bit = 0, the PCI-X interface of the bridge is in parity mode.
• If this bit = 1, the PCI-X interface of the bridge is in ECC mode.
• If the PCI bus is in ECC mode and this bit = 0, correctable errors occurring on that interface are
• If this bit = 1, correctable errors that occur on the PCI bus are not corrected and are treated as
• If this bit is 1 during a write to this configuration register, the Disable Single-Bit-Error Correction
• If this bit is 0 in a write, the Disable Single-Bit-Error Correction and ECC mode bits are not
corrected.
uncorrectable errors (including the setting of status bits and assertion of error indicator signals on
the bus).
and ECC mode bits are also updated (written).
updated.
®
Mode 1: Read-Write. PCI-X
®
2.0 Tunnel Data Sheet
Registers
®
Mode 2: Read Only. Conventional PCI: Read Only.
26792 Rev. 3.07 July 2005
Attribute: See Below
Dev[B,A]:0x70
Chapter 3