AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 83

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
PCI-X
Default: 0000 0000h
PCI-X
The values for bits 7:0 in this register are latched at the rising edge of PWROK.
Default: 0000 00??h
Chapter 3
Bits
31:0
Bits
31:24
23
22
21
20
19
18
17
16
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®
Description
These bits control no hardware.
Description
LPMARBCOUNT. Read-Write. In PCI-X
putting the PCI-X arbiter in low power mode.
LPMARBENABLE. Read-Write. Setting this bit to 1 allows the PCI-X
power mode.
Note: If this bit is set, Dev[B,A]_LPMARBCOUNT should be set to a value other than 0; otherwise results are
SERR Fatal Enable. Read-Write. When asserted, this bit causes the fatal error interrupt to be
asserted whenever Dev[B,A]:0x1C[RSE] (indicating SERR assertion detected on the secondary bus)
is asserted.
Note: There is no SERR Flood Enable because this function is covered by Dev[B,A]:0x3C[SERREN].
SERR Nonfatal Enable. Read-Write. When asserted, this bit causes the nonfatal error interrupt to be
asserted whenever Dev[B,A]:0x1C[RSE] (indicating SERR assertion detected on the secondary bus)
is asserted.
PERR Flood Enable. Read-Write. When asserted and [B,A]:0x04[SERREN] is asserted, this bit
causes the link to be flooded with sync packets whenever [B,A]:0x80[PERR_OBSERVED] is asserted.
PERR Fatal Enable. Read-Write. When asserted, this bit causes the fatal error interrupt to be
asserted whenever [B,A]:0x80[PERR_OBSERVED] is asserted.
PERR Nonfatal Enable. Read-Write. When asserted, this bit causes the nonfatal error interrupt to be
asserted whenever [B,A]:0x80[PERR_OBSERVED] is asserted.
Correctable Fatal Enable. Read-Write. When asserted, this bit causes the fatal error interrupt to be
asserted whenever a correctable error (Dev[B,A]:0x70[ECC Error Corrected] is 1 and
Dev[B,A]:0x70[ECC Error Phase] is not 0) is detected on the PCI-X
Correctable Nonfatal Enable. Read-Write. When asserted, this bit causes the nonfatal error interrupt
to be asserted whenever a correctable error (Dev[B,A]:0x70[ECC Error Corrected] is 1 and
Dev[B,A]:0x70[ECC Error Phase] is not 0) is detected on the PCI-X
Scratch
Misc II and Pins Latched at Rising Edge of PWROK
undefined.
AMD-8132™ HyperTransport™ PCI-X
®
Registers
Mode 2, this is the number of idle cycles counted prior to
®
®
bus.
bus.
®
Mode 2 arbiter to go into low
Attribute: Read-Write
®
Attribute: See Below
2.0 Tunnel Data Sheet
Dev[B,A]:0x48
Dev[B,A]:0x44
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