AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 115

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
IOAPIC Revision and Class Code
Default: A1: 0800 1001h, Bx: 0800 1011h
IOAPIC Device BIST-Header-Latency-Cache
Default: 0000 0000h
Note:
IOAPIC Base Address Low
Default: 0000 000?h
Chapter 3
Bits
31:8
7:0
Bits
31:24
23:16
15:8
7:0
Bits
31:12
11:0
IOAPIC Base Address Registers
register. Offsets 48h/4Ch are always accessible. However, offsets 10h/14h can be disabled from read
and write access through Dev[B,A]:1x44[OSVISBAR].
Description
CLASSCODE. Provides the IOAPIC class code.
REVISION. AMD-8132™ tunnel revision. 01h = revision Ax. 11h = revision B1.
Description
BIST. These bits are fixed at their default values.
HEADER. These bits are fixed at their default values.
LATENCY. These bits are fixed at their default values.
CACHE. These bits are fixed at their default values.
Description
IOAPIC Base Address Register [IOABAR] Low. Read-Write. These bits specify address space bits
[31:12] of the IOAPIC register set APIC[B,A]:XX.
Read Only.
• If Dev[B,A]:1x44[OSVISBAR] is high, these bits read 004h to indicate a 4-Kbyte block of 64-bit,
• If Dev[B,A]:1x44[OSVISBAR] is low, these bits read all 0s.
non-prefetchable memory space.
. Offsets 10h/14h and 48h/4Ch provide access to the same 8-byte
AMD-8132™ HyperTransport™ PCI-X
Registers
Dev[B,A]:1x10 and Dev[B,A]:1x48
®
Attribute: Read Only
Attribute: Read Only
Attribute: See Below
2.0 Tunnel Data Sheet
Dev[B,A]:1x0C
Dev[B,A]:1x08
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