AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 30

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
The following comparisons show the relationship between PCI-X transactions in which the relaxed ordering
bit is set and link packets:
1.3.7
Note: Where information in this section applies to both the TPS2340A and TPS2342 hot-plug
Each PCI-X bridge includes an SHPC-compliant hot-plug controller that may be used to support hot-plug
capable PCI-X or conventional PCI slots. Strapping options on [B,A]_REQ_L4 specify whether hot-plug is
supported on bridge A and bridge B. If hot-plug is supported on a bridge, then all slots connected to that bridge
are required to include hot-plug support circuitry. With the exception of a single-slot hot-plug implementation,
the hot-plug support circuitry includes one or more TPS* hot-plug power controllers, power switches, and
associated slot isolation switches to provide electrical isolation for most of the slot signals. For a single-slot
hot-plug implementation, the AMD-8132 tunnel provides the bus isolation function so only the TPS* hot-plug
power controller and the power switches are required. Each bridge supports a maximum of 4 slots when hot-
plug mode is enabled.
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• If the bus number matches the secondary bus number of the bridge, HyperTransport type 1 accesses and
• HyperTransport device messages are never claimed by the AMD-8132 tunnel.
• Downstream nonposted HyperTransport link requests to a PCI/PCI-X bus that contain non-zero SeqID
• The PCI-X no snoop bit is the inverse of the HyperTransport coherent bit for downstream memory
are not valid. When Dev[B,A]:0x40[SSS_L] is low, a config access to device 1 also causes
[B,A]_GNT_L1 to be asserted. See section 2.6.
In a system capable of operating in PCI-X Mode 2, there can only be one slot. The IDSEL signal for this
slot should be attached to [B,A]_GNT_L1, which has the alternative function of IDSEL for device 1 while
Dev[B,A]:0x40[SSS_L] is asserted (low).
extended HyperTransport type 1 accesses are forwarded onto the PCI/PCI-X bus as type 0 accesses.
If the bus number is greater than the secondary bus number of the bridge and less than or equal to the
subordinate bus number of the bridge, HyperTransport type 1 accesses and extended HyperTransport type
1 accesses are forwarded onto the PCI/PCI-X bus as type 1 accesses.
If the PCI/PCI-X bus is not operating in PCI-X Mode 2 and if an extended HyperTransport type 1 access
attempts to access a register number above 255, the operation is dropped and a response returned as if it
was master aborted on the PCI/PCI-X bus.
values are required to complete on that bus prior to initiating subsequent nonposted requests with the same
SeqID value to that PCI/PCI-X bus. Consequently, only one downstream nonposted request with each non-
zero SeqID value can be outstanding on a PCI/PCI-X bus at a time.
requests. For downstream nonmemory requests, no snoop is always be 0.
Downstream Link Transaction
A posted memory write request with PassPW
set.
A read request in which bit[3] of the command
field (response may pass posted write) is set.
A response to an upstream request.
controllers, they are referred to combinatorially as TPS* in the text.
Hot-Plug
®
2.0 Tunnel Data Sheet
Functional Operation
Corresponding PCI-X
Relaxed ordering bit of the attribute field is set.
Relaxed ordering bit of the attribute field is set.
Relaxed ordering bit of the attribute field is
copied from the attribute field of the original
request.
®
2.0 Transaction
26792 Rev. 3.07 July 2005
Chapter 1