AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 67

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Table 4.
Register fields within register locations are also identified with a name or bit group in brackets following the
register location mnemonic.
Table 5.
Chapter 3
Type
Read or
Read Only
Write
Set by Hardware
Write Once
Write 1 to clear
Write 1 only
Reserved
Note: Unless otherwise noted or described as being assigned a value at the assertion of PWROK, all registers are reset to
Base Address
Register
Dev[B,A]:1x10/48
Dev[B,A]:0x10
their default values by LDTRESET_L.
Memory Mapped Address Spaces
Register Attributes
Description
Capable of being read by software. Read Only implies that the register cannot be written
to by software.
Capable of being written by software.
Register bit is set high by hardware.
After LDTRESET_L, these registers may be written to once. After being written, they
become Read Only until the next LDTRESET_L assertion. The Write Once control is byte
based. So, for example, software may write each byte of a Write Once DWORD as four
individual transactions. As each byte is written, that byte becomes Read Only.
Software must write a 1 to the bit to clear it. Writing a 0 to these bits has no effect.
Software can set the bit high by writing a 1 to it. However, subsequent writes of 0 have no
effect. LDTRESET_L must be asserted in order to clear the bit.
For AMD internal use only. When reading Reserved bits, ignore the data. When writing to
Reserved bits, preserve the data and merge it with the write; failure to do this results in
undefined behavior.
Size
(bytes)
4K
4K
Mnemonic
APIC[B,A]:XX
SHPC[B,A]:XX
AMD-8132™ HyperTransport™ PCI-X
Registers
Registers
IOAPIC registers. Base address register at offset
10h enabled by Dev[B,A]:1x44[OSVISBAR].
Standard hot-plug controller register set.
Access is enabled by Dev[B,A]:0x48[HPEN].
Access to these registers is provided through both
memory space and configuration space. To access
through configuration space,
Dev[B,A]:0x90[SELECT] specifies the DWORD
offset and Dev[B,A]:0x94 provides the DWORD
data port.
®
2.0 Tunnel Data Sheet
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