AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 77

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
PCI-X
Default: 0000 0060h
PCI-X
Default: 0000 0?FFh
Chapter 3
Bits
31:8
7:0
Bits
31:28
27
26
25
24:23
22
21
®
®
Description
Reserved.
CAPABILITIES_PTR. Points to the next capability block. See Dev[B,A]:0x60.
Description
Reserved.
Discard Timer Sync Flood Enable [DTSE]. Read-Write. If Dev[B,A]:0x3C[DTS] is high and this bit is
set, indicate an error as follows:
Discard Timer Status [DTS]. Read. Set by hardware. Write 1 to clear.
1 = The secondary discard timer discard timer timed out. This bit is not capable of being set when the
Note: This bit is cleared by PWROK reset but not by LDTRESET_L.
Secondary Discard Timer [SDT]. Read-Write. This bit is used to decrease the number of clocks
used by the PCI-defined discard timer.
0 = Discard timer times out after 32K PCLK cycles.
1 = Discard timer times out after 1K PCLK cycles.
Reserved.
Secondary Bus Reset [SBRST]. Read-Write.
0 = [B,A]_RESET_L not asserted.
1 = [B,A]_RESET_L asserted; secondary PCI bus placed into reset state.
Master Abort Response [MARSP]. Read-Write.
0 = Master aborts to nonposted requests result in normal responses on the originating bus. Read
1 = The responses to nonposted requests that come from the host bus or secondary bus that result in
Bridge Capabilities Pointer
Bridge Interrupt and Bridge Control
• If Dev[B,A]:0x04[SERREN] is asserted and Dev[B,A]:0x40[PCIErrorSerrDisable] is deasserted,
• If Dev[B,A]:0x40[PCIErrorNonfatalEn] or Dev[B,A]:0x40[PCIErrorFatalEn] is asserted, then assert
then Dev[B,A]:0x04[SSE] is set and the links are flooded with sync packets.
the nonfatal or fatal signal respectively.
secondary bus is in PCI-X
responses are sent with the appropriate amount of data, which are all 1s. Posted requests from
HyperTransport™ that are master aborted on PCI/PCI-X
master aborts indicate a target abort to the initiating bus (through PCI bus protocol or link
protocol). Master aborts on PCI/PCI-X result in the assertion of
Dev[B,A]:0x80[DISCARDED_POST].
®
mode.
AMD-8132™ HyperTransport™ PCI-X
Registers
®
are silently dropped.
®
Attribute: Read Only
Attribute: See Below
2.0 Tunnel Data Sheet
Dev[B,A]:0x3C
Dev[B,A]:0x34
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