AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 78

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
DevB:0x40
78
20
19
18
17
16
15:8
7:0
VGA 16 Bit Decode [VGA16DEC]. Read-Write. Resets to 0.
See bit 19, [VGAEN].
VGA Decoding Enable [VGAEN]. Read-Write.
0 = The AMD-8132™ tunnel does not decode VGA-compatible address ranges.
1 = Route host-initiated commands targeting VGA-compatible address ranges to the secondary bus.
ISA Decoding Enable [ISAEN]. Read-Write.
0 = The PCI I/O window is the whole range specified by Dev[B,A]:0x1C[15:0] and Dev[B,A]:0x30.
1 = The I/O address window specified by Dev[B,A]:0x1C[15:0] and Dev[B,A]:0x30 is limited to the first
System Error Enable [SERREN]. Read-Write. If this bit is set and Dev[B,A]:0x04[SERREN] is set
and Dev[B,A]:0x1C[RSE] is set (indicating that SERR assertion has been detected on the secondary
bus), then the AMD-8132 tunnel responds by flooding both outgoing HyperTransport™ links with sync
packets and setting Dev[B,A]:0x04[SSE].
Uncorrectable Error Response Enable [PEREN]. Read-Write. Enables setting
Dev[B,A]:0x1C[MDPE] in response to uncorrectable errors on the local PCI/PCI-X
See Chapter 5 Error Conditions and Handling.
INTERRUPT_PIN. Read Only.
Note: When hot-plug mode is enabled, [B,A]_PIRQA_L can be asserted for hot-plug events.
INTERRUPT_LINE. Read-Write. These bits control no internal logic.
• If set, bits [15:10] are compared when decoding VGA-compatible I/O addresses.
• If clear, address bits [15:10] are ignored; allowing VGA-compatible I/O addresses to alias through
• If Dev[B,A]:0x48[HPEN] is low, then Dev[B,A]:0x3C[INTERRUPT_PIN] is 00h.
• If Dev[B,A]:0x48[HPEN] is high, then Dev[B,A]:0x3C[INTERRUPT_PIN] is 01h.
the first 64 Kbytes of I/O space.
These include memory accesses from A0000h to BFFFFh and I/O accesses in which address bits
[9:0] range from 3B0h to 3BBh or 3C0h to 3DFh. If Dev[B,A]:0x3C[VGA16DEC] is asserted, bits
[15:10] are 0. If Dev[B,A]:0x3C[VGA16DEC] is clear, bits [15:10] are ignored in the decode. Bits
[31:16] are 0. Secondary bus accesses to these ranges are not claimed by the AMD-8132 tunnel.
256 bytes of each 1-Kbyte block specified; this only applies to the first 64 Kbytes of I/O space.
®
2.0 Tunnel Data Sheet
Registers
26792 Rev. 3.07 July 2005
®
bus.
Chapter 3