AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 134

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
3.7
These registers are accessed through either indexed configuration space (see Dev[B,A]:0x90[SELECT] and
Dev[B,A]:0x94[DATA]) or non-indexed memory space (see SHPC[B,A]:00). All accesses (reads or writes) to
SHPC registers must fit within a 32-bit aligned block. Accesses that span multiple 32-bit blocks result in
undefined behavior.
SHPC Base Offset
Default: 0000 0000h
SHPC Slots Available I
Default: 0000 0000h
134
Bits
31:0
Bits
31:29
28:24
23:21
20:16
15:13
12:8
7:5
4:0
• If Dev[B,A]:0x48[HPEN] = 0 then the SHPC[B,A]:XX registers are all reserved.
• See section 3.1.2 for a description of the register naming convention.
• See the TPS* hot-plug power controller product data sheets for more information.
Description
BASE_OFFSET. This register is hardwired low to indicate the memory space base address of the
SHPC register set is specified only by Dev[B,A]:0x10[SHPCBAR].
Description
Reserved.
N_133PCIX. Indicates the maximum number of hot-plug slots available to be enabled when the bus is
running at 133 MHz in PCI-X
Reserved.
N_100PCIX. Indicates the maximum number of hot-plug slots available to be enabled when the bus is
running at 100 MHz in PCI-X mode.
Reserved.
N_66PCIX. Indicates the maximum number of hot-plug slots available to be enabled when the bus is
running at 66 MHz in PCI-X mode.
Reserved.
N_33CONV. Indicates the maximum number of hot-plug slots available to be enabled when the bus is
running at 33 MHz in conventional PCI mode.
SHPC Working Registers
®
mode.
®
2.0 Tunnel Data Sheet
Registers
26792 Rev. 3.07 July 2005
Attribute: Write Once
Attribute: Read Only
SHPC[B,A]:00
SHPC[B,A]:04
Chapter 3