AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 136

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
SHPC Secondary Bus Configuration
Default: 0?00 0?00h
SHPC Command and Status
For bits [19:16] of this register, the Controller Command Error Code field consists of
SHPC[B,A]:14[INVSM_ERR, INVCMD_ERR, MRLO_ERR]. No bits or one bit of the Controller Command
136
12:8
7:5
4:0
Bits
31:24
23:9
8
7:4
3:0
First Device Number [FDN]. Specifies the device number assigned to the first hot-plug slot on the
secondary bridge bus.
Reserved.
Number Of Slots Implemented [NSI]. Specifies the number of hot-plug slots on the bridge.
Description
SHPC Programming Interface. Identifies the format of the SHPC working register set. The value
read is 2 unless Dev[B,A]:0x48[SHPC_PI_1] = 1, in which case the value read is 1.
Reserved.
If Dev[B,A]:0x48[SHPC_PI_1] is a 0, this reads 1 indicating that this device supports Mode 1 ECC.
If Dev[B,A]:0x48[SHPC_PI_1] is a 1, this is reserved and reads 0.
Reserved.
MODE. Indicates the current speed and mode at which the secondary bridge bus operates. MHz
value below is the common clock.
Notes:
1011b through 1111b are Reserved.
Encoding
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1. See Dev[B,A]:0x48[PSLOW] for nominal speed settings of 33 or 66 MHz running at 25 or 50 MHz.
2. If Dev[B,A];0x48[SHPC_PI_1] is a 1, modes 0101b through 1010b are not valid.
Speed MHz
100
33/25
66/50
66/50
100
133
66/50
100
133
66/50
100
133
66/50
133
®
2.0 Tunnel Data Sheet
Registers
Mode
Conventional PCI
Conventional PCI
PCI-X
PCI-X Mode 1 with parity
PCI-X Mode 1 with parity
PCI-X Mode 1 with ECC
PCI-X Mode 1 with ECC
PCI-X Mode 1 with ECCN/A
PCI-X Mode 2 ECC
PCI-X Mode 2 ECC
PCI-X Mode 2 ECCDDR
PCI-X Mode 2 ECC
PCI-X Mode 2 ECCQDR
PCI-X Mode 2 ECC
®
Mode 1 with parity
26792 Rev. 3.07 July 2005
QDR
N/A
N/A
N/A
N/A
N/A
N/A
DDR
DDR
QDR
Data Transfer Rate
N/A
Attribute: Read Only
SHPC[B,A]:10
SHPC[B,A]:14
Chapter 3