AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 148

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
4.2.4
Bridges in hot-plug mode are always placed into 33 MHz conventional PCI mode after LDTRESET_L is
asserted. The operational speed and mode are then initialized by software through the following steps:
This sequence is the same when hot-plug single-slot support is selected (Dev[B,A]:0x40[SSS_L]). However,
all of the slot signals are forced low until the slot is powered.
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• Up to 5 sets of REQ_L, GNT_L, and PCLK may be functionally active in PCI-X Mode 1. However, 5 slots are only
• If a bridge from the AMD-8132 tunnel supports PCI-X Mode 2 operations, then there must be a single PCI/PCI-X slot.
• The state of the straps is reflected in Dev[B,A]:0x60[SCF] and Dev[B,A]:0x40[CPCI66] after a cold reset.
• If the systemboard supports PCI-X mode operation for a bridge, then a pullup resistor to VDD33 must be placed on the
1. Initialization of Write Once registers in the SHPC[B,A]:XX register block.
2. Optional execution of Power Only All Slots SHPC command.
3. Acquisition of the capabilities and presence information for each slot by observing the RST_L, M66EN,
4. Determination of the highest common bus frequency and mode that may be selected.
5. Execution of Set Bus Segment Speed/Mode SHPC command for the selected speed and mode.
6. Execution of Enable All Slots SHPC command.
electrically, but all 5 sets of REQ_L, GNT_L, and PCLK signals are available. In this case the motherboard design can
choose from any of the 5 sets of signals, and BIOS should turn off the unused PCLK outputs.
supported electrically if in 33 MHz conventional PCI. If there are 5 slots, M66EN and PCIXCAP should be grounded on
the systemboard to the slots so all PCI cards properly initialize.
This slot must have the MODE2 pin asserted. SSS_L for this bridge must also be asserted (i.e., the AMD-8132 tunnel
must know there is only one slot on this bus). IDSEL for this slot must be connected to [B,A]_GNT_L1 rather than to an
AD line (PCI-X Mode 2 operation requires IDSEL lines to be distinct signals, not shared with AD signals). The power
supply must be capable of providing 1.5 or 3.3 V to VIO[B,A] and must use [B,A]_REQ_L1 ([B,A]_VIOSEL) and
[B,A]_PCLK[1] ([B,A]_VIOEN) to control the VIO[B,A] voltage. See section 7.1.4.
bridge PCIXCAP pin. To limit the frequency of a PCI-X-capable bridge to 66 MHz on a systemboard, the systemboard
must also include a pulldown resistor from the bridge PCIXCAP pin to ground and must not indicate there is a single
slot present (i.e., SSS_L must not be asserted). The strapping options on GNT_L[1] are used to distinguish between
systems that support 100MHz and 133 MHz. In either of these two cases, the systemboard should include no pulldown
resistors on PCIXCAP.
PCIXCAP, PRSNT1_L, and PRSNT2_L signals.
Hot-Plug Initialization
®
2.0 Tunnel Data Sheet
Clocks and Reset
26792 Rev. 3.07 July 2005
Chapter 4