AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 143

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 4
4.1
REFCLK_[H,L] is required to be running for the AMD-8132™ HyperTransport™ PCI-X
operate. The AMD-8132 tunnel provides [B,A]_PCLK[4:0] as the clocks to the secondary bus devices.
4.1.1
The AMD-8132 tunnel provides:
[B,A]_PLLCLKO and [B,A]_PCLK[4:0] run at the specified secondary bus frequency.
The systemboard is required to include a loopback connection from [B,A]_PLLCLKO to [B,A]_PLLCLKI.
The length of this connection is required to be approximately the same as the length of the [B,A]_PCLK traces
from the AMD-8132 tunnel to the external PCI devices so the flight time of the [B,A]_PCLK signals is the
same as the flight time of the PLL feedback.
Flight time is defined as the time difference between the rising edge of the clock as observed at the source of
the systemboard trace [B,A]_PLLCLKO and [B,A]_ PCLK at the AMD-8132 tunnel, and the rising edge of the
clock as observed at the destination of the systemboard trace [B,A]_PLLCLKI at the AMD-8132 tunnel and
[B, A]_PCLK at the external device, as shown in Figure 19. The AMD-8132 tunnel is so designed for the
purposes of meeting AC timing requirements. If the PCLK flight time matches the PLL feedback flight time,
then PCLK as observed at the destination is equivalent to the PCI-defined PCLK signal to the
AMD-8132 tunnel. Accordingly, the PLL feedback flight time is required to be the same as any of the PCLK
trace flight times (for a bridge), within the skew limits specified by the PCI specifications for PCLK to
different devices: 2 ns for conventional PCI 33 MHz; 1 ns for conventional PCI 66 MHz; 0.5 ns for all PCI-X
mode frequencies.
Chapter 4
• The PCI clocks for secondary bus devices, [B,A]_PCLK[4:0].
• A PLL feedback for itself, [B,A]_PLLCLKO to [B,A]_PLLCLKI.
• The length of the connection from A_PLLCLKO to A_PLLCLKI should be the same as the length of the
• The length of the connection from B_PLLCLKO to B_PLLCLKI should be the same as the length of the
A_PCLK signals.
B_PCLK signals.
Clocking
Systemboard Requirements
Clocks and Reset
Clocks and Reset
AMD-8132™ HyperTransport™ PCI-X
®
2.0 Tunnel Data Sheet
®
2.0 tunnel to
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