AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 141

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
SHPC Logical Slot
The offset for the SHPC LSR (Logical Slot Register) for slot 1 is 24h, for slot 2 is 28h, for slot 3 is 2Ch, and for
slot 4 is 30h. The LSR is used instead of SHPC[B,A]:[30, 2C, 28, 24] in the description below. See
SHPC[B,A]:20 for information about how these registers may affect interrupts, events, and system errors.
Default: 7F00 3F3Fh
Chapter 3
1
0
Bits
31
30
29
28
27
26
25
24
23:21
20
19
18
17
Global SERR Mask [GSERRM]. Read-Write.
1 = SERR indication is disabled.
Global Interrupt Mask [GIM]. Read-Write.
1 = SHPC interrupt generation is disabled.
Description
Reserved.
Connected Power Fault SERR Mask [CPF_SERRM]. Read-Write.
0 = SERR generation is enabled when LSR[CPF_STS] is set.
1 = SERR generation is disabled when LSR[CPF_STS] is set.
MRL Sensor SERR Mask [MRLS_SERRM]. Read-Write.
0 = SERR generation is enabled when LSR[MRLSC_STS] is set.
1 = SERR generation is disabled when LSR[MRLSC_STS] is set.
Connected Power Fault Interrupt Mask [CPF_IM]. Read-Write.
0 = Interrupt generation is enabled when LSR[CPF_STS] is set.
1 = Interrupt generation is disabled when LSR[CPF_STS] is set.
MRL Sensor Interrupt Mask [MRLS_IM]. Read-Write.
0 = Interrupt generation is enabled when LSR[MRLSC_STS] is set.
1 = Interrupt generation is disabled when LSR[MRLSC_STS] is set.
Attention Button Interrupt Mask [AB_IM]. Read-Write.
0 = Interrupt generation is enabled when LSR[ABP_STS] is set.
1 = Interrupt generation is disabled when LSR[ABP_STS] is set.
Isolate Power Fault Interrupt Mask [IPF_IM]. Read-Write.
0 = Interrupt generation is enabled when LSR[IPF_STS] is set.
1 = Interrupt generation is disabled when LSR[IPF_STS] is set.
Card Presence Interrupt Mask [CP_IM]. Read-Write.
0 = Interrupt generation is enabled when LSR[CPC_STS] is set.
1 = Interrupt generation is disabled when LSR[CPC_STS] is set.
Reserved.
Connected Power Fault Status [CPF_STS]. Read. Set by hardware. Write 1 to clear. Set when
LSR[PF] changes from 0 to 1 while LSR[SS] = 10b (slot is enabled).
MRL Sensor Change Status [MRLSC_STS]. Read. Set by hardware. Write 1 to clear. Set when
LSR[MRLS] changes its value.
Attention Button Press Status [ABP_STS]. Read. Set by hardware. Write 1 to clear. Set when
LSR[AB] transitions from 0 to 1.
Isolated Power Fault Status [IPF_STS]. Read. Set by hardware. Write 1 to clear. Set when LSR[PF]
changes from 0 to 1 while LSR[SS] ! = 10b (slot is not in the enabled state).
AMD-8132™ HyperTransport™ PCI-X
Registers
SHPC[B,A]:[30,2C,28,24]
®
Attribute: See Below
2.0 Tunnel Data Sheet
141