AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 75

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Dev[B,A]:0x1C
Default: 0220 01F1h
Chapter 3
Bits
31
30
29
28
27
26:25
24
23
22:16
15:12
11:8
7:4
3:0
Description
Detected Uncorrectable Error [DPE]. Read. Set by hardware. Write 1 to clear. Set if the
AMD-8132™ tunnel detects an uncorrectable error on the PCI-X
cycle, or while accepting read data or write data.
Note: This bit is cleared by PWROK reset but not by LDTRESET_L.
Received System Error [RSE]. Read. Set by hardware. Write 1 to clear.
1 = The AMD-8132 tunnel detected either [B,A]_SERR_L or [B,A]_SHPC_SERR asserted. In order to
Note: This bit is cleared by PWROK reset but not by LDTRESET_L.
Received Master Abort [RMA]. Read. Set by hardware. Write 1 to clear.
1 = The AMD-8132 tunnel received a master abort as a master on the secondary bus.
Note: This bit is cleared by PWROK reset but not by LDTRESET_L.
Received Target Abort [RTA]. Read. Set by hardware. Write 1 to clear.
1 = The AMD-8132 tunnel received a target abort as a master on the secondary PCI bus.
Note: This bit is cleared by PWROK reset but not by LDTRESET_L.
Signalled Target Abort [STA]. Read. Set by hardware. Write 1 to clear.
1 = The AMD-8132 tunnel generated a target abort as a target on the secondary PCI bus.
Note: This bit is cleared by PWROK reset but not by LDTRESET_L.
Device Select Timing. Read Only. These bits are hardwired to indicate medium decoding speed.
Master Data Uncorrectable Error [MDPE]. Read. Set by hardware. Write 1 to clear.
1 = The AMD-8132 tunnel sets this bit if Dev[B,A]:0x3C[PEREN] is set and one of these conditions
Note: This bit is cleared by PWROK reset but not by LDTRESET_L.
Fast Back-to-Back Enable [FBBEN]. Read Only. This bit is fixed low, indicating the
AMD-8132 tunnel does not support fast back-to-back transactions.
Read Only. These bits are fixed in their default state.
IO Limit Address [IOLIM]. Address bits[15:12]. See Dev[B,A]:0x[30:1C].
Read Only. Returns 0001 indicating the I/O upper limit is implemented.
IO Base Address [IOBASE]. Address bits[15:12]. See Dev[B,A]:0x[30:1C].
Read Only. Returns 0001 indicating the I/O upper base is implemented.
clear this bit, these signals must be deasserted.
occurs:
• An uncorrectable error is detected during a data phase of a read.
• The detection of [B,A]_PERR_L asserted during a write as a master on the secondary bus.
AMD-8132™ HyperTransport™ PCI-X
Registers
®
bus during an address/attribute
®
Attribute: See Below
2.0 Tunnel Data Sheet
75