AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 90

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
PCI-X
Default: A1: 0003 0000h, Bx: 0003 0008h
90
19
18
17
16
15:8
7:0
Bits
31:30
29
28:22
21
20
19
18
17
16
15:8
7:3
2:0
®
Unexpected Split Completion [USC]. Read Only. Always 0.
Default = 0
Split Completion Discarded [SCD]. Read. Set by hardware. Write 1 to clear.
1 = The bridge discarded a split completion moving toward the secondary bus because the requester
Default = 0
Note: Cleared by PWROK, not LDTRESET_L.
133 MHz Capable. Read Only. This bit is hardwired high to indicate support for 133 MHz.
64-bit Device. Read Only. The value of this register is the inverse of Dev[B,A]:0x40[DIS64].
Capabilities Pointer. Read Only. Points to the next capability block. See Dev[B,A]:0x[BC,B8].
Capability ID. Read Only. Specifies the capability ID for PCI-X
Description
Reserved.
Device ID Messaging Capable. Read Only. This bit is zero, indicating the bridge does not forward
Device ID Messages between the primary and secondary interfaces.
Reserved.
Split Request Delayed [SRD]. Read Only. Hardwired low. The AMD-8132™ tunnel automatically
limits the number of downstream PCI-X
so there is no reason to limit the number of ADQs in read requests it accepts.
Split Completion Overrun. Read Only. This bit is hardwired low; it has no meaning since the primary
bus is not PCI-X
Unexpected Split Completion. Read Only. This bit is hardwired low; it has no meaning since the
primary bus is not PCI-X
Split Completion Discarded. Read Only. This bit is hardwired low; it has no meaning since the
primary bus is not PCI-X
133 MHz Capable. This bit is set high arbitrarily; it has no meaning since the primary bus is not
PCI-X
64-bit Device. Read Only. This bit is set high arbitrarily; it has no meaning since the primary bus is not
PCI-X
Bus Number. Read Only. These bits reflect the state of Dev[B,A]:0x18[PRIBUS].
Device Number. Read Only. For DevA, these bits reflect the state of DevA:0xC0[BUID]. For DevB,
these bits reflect the state of DevA:0xC0[BUID] plus 1.
Function Number. Read Only. This is 0h to reflect the value of this function.
Bridge Status
would not accept it.
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2.0 Tunnel Data Sheet
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read requests to the number of upstream buffers available;
Registers
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configuration space.
26792 Rev. 3.07 July 2005
Attribute: See Below
Dev[B,A]:0x64
Chapter 3