AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 66

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
into bits[15:11] of the configuration address. The function number is mapped into bits[10:8] of the
configuration address. The offset is mapped to bits[7:0] of the configuration address.
The address space for the AMD-8132 tunnel configuration space can be reached with either a HyperTransport
type 0 access, or with an extended HyperTransport type 0 access. When using an extended type 0 access, all
registers with an address above 255 bytes are reserved.
The following diagram shows the devices in configuration space as viewed by software.
Figure 18. Configuration Space.
Device A, above, is programmed to be DevA:0xC0[BUID] and device B is DevA:0xC0[BUID] plus 1. See the
Link Command register for details. Also see section 1.3.5 HyperTransport™ Requests Claimed by the
Bridges.
3.1.2
Configuration register locations are referenced with mnemonics that take the form of Dev[A|B]:[7:0]x[FF:0],
where the first bracket contains the device, the second bracket contains the function number, and the last
bracket contains the offset.
The AMD-8132 tunnel does not claim configuration register accesses to unimplemented functions within its
devices, they are forwarded to the other side of the tunnel. Accesses to unimplemented register locations within
implemented functions are claimed, those registers are Reserved.
Table 3.
Other register locations (e.g., memory mapped registers) are referenced with an assigned mnemonic that
specifies the address space and offset. These mnemonics start with four characters that identify the space
followed by characters that identify the offset within the space.
66
Device Function Mnemonic
A
A
B
B
PCI-X
External
Devices
0
1
0
1
®
Register Naming and Description Conventions
Bus
Register Naming Conventions
DevA:0xXX
DevA:1xXX
DevB:0xXX
DevB:1xXX
Device Header
First Device
DevA:1xXX
Function 1
IOAPIC
Secondary Bus
PCI-X
Registers
PCI-PCI bridge A registers; link and PCI-X
IOAPIC for PCI-X
PCI-PCI bridge B registers; PCI-X
IOAPIC for PCI-X
Bridge Header
®
First Device
DevA:0xXX
Function 0
2.0 Tunnel Data Sheet
®
Bridge
Registers
PCI-X
®
®
Second Device
Bridge Header
Primary Bus
bridge A.
bridge B.
DevB:0xXX
Function 0
®
Bridge
Secondary Bus
®
Second Device
Device Header
capabilities block.
DevB:1xXX
Function 1
IOAPIC
®
capabilities block.
26792 Rev. 3.07 July 2005
PCI-X
External
Devices
®
Chapter 3
Bus