AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 107

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Link Revision, Errors, and Frequency Capability 0
Default: A1: 007D 0025h, Bx: 007D 0040h
Feature, Link Errors, and Frequency Capability 1
Default: 007D 0012h
Chapter 3
Bits
31:16
15
14
13
12
11:8
7:0
Bits
31:16
15
14
Description
Link 0 Frequency Capability [FREQCAP0]. Read Only. These bits indicate that side 0 of the tunnel
supports 200, 400, 500, 600, 800, and 1000 MHz link frequencies.
CTL Timeout. Read-Write. Resets to 0. This bit indicates how long CTL can be low before indicating
a protocol error. A value of 0 in this bit = one millisecond; a value of 1 = one second.
End of Chain Error. Read. Write 1 to clear. This bit indicates that a posted request or response
packet has been given to this transmitter to issue when link 0 is the end of chain or a 64-bit posted
request reaches link 0 with 64-bit support disabled. Receiving a device message with the silent drop
bit set does not set this bit.
Note: This bit is cleared by PWROK reset, not by LDTRESET_L.
Overflow Error. Read. Write 1 to clear. This bit indicates a receive buffer overflow error has been
detected on link 0.
Note: This bit is cleared by PWROK reset, not by LDTRESET_L.
Protocol Error. Read. Write 1 to clear. This bit indicates a protocol error has been detected on link 0.
Note: This bit is cleared by PWROK reset, not by LDTRESET_L.
Link 0 Frequency [FREQ0]. Read-Write. Specifies the link side 0 transmit frequency. Legal values
are 0h (200 MHz), 2h (400 MHz), 3h (500 MHz), 4h (600 MHz), 5h (800 MHz), and 6h (1000 MHz).
Note: This bit is cleared by PWROK reset, not by LDTRESET_L. After this field is updated, the link frequency
REVISION. Read Only. Indicates to which rev of the HyperTransport™I/O Link Specification the
AMD-8132™ tunnel is compliant.
Note: Rev A1 of the AMD-8132 tunnel only indicates support for HyperTransport™I/O Link Specification, Rev 1.05.
Description
Link 1 Frequency Capability [FREQCAP1]. Read Only. These bits indicate that side 1 of the tunnel
supports 200, 400, 500, 600, 800, and 1000 MHz link frequencies.
CTL Timeout. Read-Write. Resets to 0. This bit indicates how long CTL can be low before indicating
a protocol error. A value of 0 in this bit = one millisecond; a value of 1 = one second.
End of Chain Error. Read-Write. Write 1 to clear. This bit indicates that a posted request or response
packet has been given to this transmitter to issue when link 1 is the end of chain or a 64-bit request
reaches link 1 with 64-bit support disabled. Receiving a device message with the silent drop bit set
does not set this bit.
Note: This bit is cleared by PWROK reset, not by LDTRESET_L.
does not change until either LDTRESET_L is asserted or a link disconnect sequence occurs through
LDTSTOP_L.
AMD-8132™ HyperTransport™ PCI-X
Registers
®
Attribute: See Below
Attribute: See Below
2.0 Tunnel Data Sheet
DevA:0xCC
DevA:0xD0
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