AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 130

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
130
7
6
5
4
3
2
1
Tunnel Destination.
Default = 0
Note: If Control[1] = 0, this bit affects Control[17:10].
Count Clocks.
Default = 0
Assert Nonfatal Interrupt on Counter Overflow.
Default = 0
Note: Overflow for the 32- or 36-bit counter is defined by Control[2].
Counter Port Select. Port selects are as follows:
Default = 0
Counter Overflow. Write 1 to clear.
Default = 0
Note:
If the Counter Domain Select = 0, the count wraps to zero after FFFF_FFFFh and sets the overflow bit.
If the Counter Domain Select = 1, the count wraps to zero after F_FFFF_FFFFh and sets the overflow bit.
Counter Domain Select.
Default = 0
Select PCI/PCI-X
Default = 0
• If Control[1] = 0 and this bit is set to 0, counting operations whose destination is the far (other side
• If Control[1] = 1, this bit is Reserved.
• If this bit is set to 0, count information is determined by other Control bits.
• If this bit is set to 1, only the total number of clocks since the counter was cleared are counted. So,
• If this bit is set to 0, asserting a nonfatal interrupt on a counter overflow is disabled.
• If this bit is set to 1, asserting a nonfatal interrupt on a counter overflow is enabled.
• If Control[1] = 0 and this bit is set to 0, HyperTransport™ link 0 is selected.
• If Control[1] = 1 and this bit is set to 0, PCI/PCI-X
• If this bit is 0, the counter has not wrapped.
• If this bit is 1, the counter has wrapped.
• If this bit is set to 0, the DevA:1x[A0,A4] Counter CSR displays counter bits[31:0]. The count wraps
• If this bit is set to 1, the DevA:1x[A0,A4] Counter CSR displays counter bits[35:4]. The count wraps
• If this bit is set to 0, the counter counts information from HyperTransport™ link 0 or link 1.
• If this bit is set to 1, the counter counts information from PCI/PCI-X
of the chip) transmitter is disabled.
If Control[1] = 0 and this bit is set to 1, counting operations whose destination is the far (other side
of the chip) transmitter is enabled.
if this bit is 1 and
If Control[1] = 0 and this bit is set to 1, HyperTransport™ link 1 is selected.
If Control[1] = 1 and this bit is set to 1, PCI/PCI-X
to zero after FFFF_FFFFh and sets the Control[3] counter overflow bit. A write to the Counter CSR
writes bits [31:0] and always clears the Control[3] counter overflow bit.
to zero after F_FFFF_FFFFh and sets the Control[3] counter overflow bit. A write to the Counter
CSR writes bits [35:4], sets bits [3:0] to zero, and always clears the Control[3] counter overflow bit.
if Control[1] = 0, core clocks are counted.
if Control[1] = 1, PCI/PCI-X
if Control[6] = 1, Control[30:7] are unused.
®
.
®
®
2.0 Tunnel Data Sheet
bus A clocks are counted.
Registers
®
®
bus B is selected.
bus A is selected.
®
bus A or bus B.
26792 Rev. 3.07 July 2005
Chapter 3