AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 28

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
The bridges never claim a HyperTransport device message.
If the COMPAT bit is set and DevA:0x48[COMPAT] = 1, then all memory space, I/O space, and interrupt
acknowledge requests are claimed and passed to bridge A.
If the COMPAT bit is set in the transaction and DevA:0x48[COMPAT] = 0, then per the HyperTransport link
protocol the AMD-8132 tunnel never claims the transaction. Such transactions are automatically passed to the
other side of the tunnel or master aborted if the AMD-8132 tunnel is at the end of the chain.
1.3.6
1.3.6.1
The following are general considerations for AMD-8132 tunnel transactions:
1.3.6.2
While in conventional PCI mode or PCI-X Mode 1, the upper half of the PCI bus [B,A]_AD[63:32],
[B,A]_CBE_L[7:4], and [B,A]_PAR64, is pulled high with weak pullups per PCI Local Bus Specification, Rev
2.3, section 3.8.1. These pullups are disabled for PCI-X Mode 2 or if Dev[B,A]:0x40[DISPU] is asserted.
1.3.6.3
The following apply to AMD-8132 tunnel upstream transactions:
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• All EOI broadcasts.
• All Stop Grant and STPCLK broadcasts (see section 4.1.2).
• The PCIXCAP pins are implemented as described in PCI-X Protocol Addendum to the PCI Local Bus
• PCI cache line wrap mode is not supported. If a transaction is initiated that indicates this protocol, it is
• PCI-X transactions that cross address space boundaries as defined by the window configuration registers
• If there is a downstream nonposted request to PCI-X that results in a device-specific error in a completion
• When the AMD-8132 tunnel asserts [B,A]_DEVSEL_L, it does so as a medium decode speed device in
• If there is a HyperTransport transaction to I/O or configuration space that targets one of the bridges or is
• The AMD-8132 tunnel requires two HyperTransport-defined UnitIDs. The first UnitID applies to bridge
Specification, Rev 2.0a.
disconnected at the cacheline boundary.
Dev[B,A]:0x[30:1C] result in undefined behavior.
message, then the response passed to the link indicates a target abort.
conventional PCI mode and decode speed B device in PCI-X Mode 1 and Mode 2.
claimed by that bridge and it crosses a naturally aligned doubleword (dword) boundary, then the
AMD-8132 tunnel does not send the transaction to the bus and the HyperTransport response is a target
abort. Any I/O or config transactions not claimed by the AMD-8132 tunnel are forwarded to the next
device on the HyperTransport chain, regardless of the alignment and length.
A. The second UnitID applies to bridge B and is contained in the following HyperTransport transactions:
• External master requests associated with the bridge.
• Interrupt requests associated with the bridge.
• Responses to host-initiated requests that enter the address space of the bridge including
configuration registers (DevA registers for bridge A and DevB registers for bridge B); secondary I/O
Transaction Considerations
General
Pullups on Upper PCI Bus
Upstream Transactions
®
2.0 Tunnel Data Sheet
Functional Operation
26792 Rev. 3.07 July 2005
Chapter 1