AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 153

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
5.2.2
5.2.2.1
PCI-X MemRdDWORDs and PCI/PCI-X I/O reads and writes are required to have address bits [1:0] match the
least-significant asserted byte enable in the request. When the AMD-8132 tunnel is the target of such a request,
and the address and byte enables do not match, the AMD-8132 tunnel responds with an immediate target abort.
5.2.2.2
When the starting address of a PCI-X read burst indicates the AMD-8132 tunnel is the target, but the byte
count carries the transaction across an address range boundary, the AMD-8132 tunnel splits the transaction and
returns read data up to the boundary. It then issues a split completion error message of PCI-X Bridge Error
(Class 1), Target Abort (index 01h). Write bursts in all modes and conventional PCI reads don't need to return
errors for this case. They simply disconnect at the boundary, allowing the re-issued transaction to master abort
if no other device responds. Range boundaries that are checked include:
5.2.3
Whenever the AMD-8132 tunnel detects the assertion of [B,A]_PERR_L by any device on the PCI/PCI-X bus,
including itself, it sets the Dev[B,A]:0x80[0] PERR_OBSERVED bit.
Additional action may be taken on [B,A]_PERR_L assertion if it was driven in response to data driven by the
AMD-8132 tunnel. The specific action depends on which type of operation the AMD-8132 tunnel was driving,
as described in the following subsections.
5.2.3.1
If [B,A]_PERR_L is asserted on posted write data from the AMD-8132 tunnel that the AMD-8132 tunnel did
not intentionally poison, and the Dev[B,A]:0x3C[16] Uncorrectable Error Response Enable (PEREN) in the
Bridge Control CSR is set, the AMD-8132 tunnel sets the Dev[B,A]:0x80[1] DISCARDED_POST bit in the
Misc Bridge Errors CSR. If [B,A]_PERR_L is asserted for posted write data that the AMD-8132 tunnel put out
poisoned, no additional action is taken.
If the Dev[B,A]:0x48[15] CLEARPCILOG_L bit is set, DISCARDED_POST only pulses high for a single
cycle, rather than remaining high. DISCARDED_POST can be mapped to cause sync flooding by clearing
Dev[B,A]:0x40[21] PciErrorSerrDisable, or to fatal/nonfatal interrupt assertion by setting
Dev[B,A]:0x40[22,23] PciErrorFatalEn/PciErrorNonFatalEn.
Chapter 5
• PERR_OBSERVED can be mapped to cause sync flooding by setting the Dev[B,A]:0x48[20] PERR Flood
• PERR_OBSERVED can be mapped to fatal/nonfatal error interrupt assertion by setting the
Enable bit.
Dev[B,A]:0x48[19,18] PERR Fatal/Nonfatal Enable bits.
• top of 64-bit memory address space;
• top of 40-bit memory address space (FD_0000_0000h);
• nonprefetchable memory base, if enabled (Dev[B,A]:0x[D8,20]);
• prefetchable memory base, if enabled (Dev[B,A]:0x[28,24]);
• base of VGA memory space, if enabled (A_0000h).
Addressing Errors
Address/Byte Enable Mismatch
Bursts Across Address Range Boundaries
PERR_L Assertion
PERR_L Assertion on Posted Write Data
Error Conditions and Handling
AMD-8132™ HyperTransport™ PCI-X
®
2.0 Tunnel Data Sheet
153