AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 14

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
Acronyms and Terms
14
Acronym/Term
ADQ
Cell
CFF
DDR
DEST
DM
DS
DW
GCM
IM
IOAPIC
IRR
IV
LI
LR[0,1]
LT[0,1]
Link
MT
PD
PHY
POL
PU
RDR
SDR
SHPC
TM
A 128-byte aligned data quantum as defined by the PCI-X specification, rev 2.0a.
32 bits of CAD aligned to a 32-bit boundary in the HyperTransport™ protocol with asso-
ciated CTL bit.
Clock Forwarding FIFO.
In the case of PCI-X
Destination.
Interrupt destination mode.
Downstream, away from the host bridge. Also Delivery Status.
32 bits.
Link interface cycle manager.
Interrupt Mask.
I/O Advanced Programmable Interrupt Controller.
Interrupt Request Register.
Interrupt Vector.
AMD-8132™ tunnel HyperTransport™ interface. This interface is the data/command
transfer mechanism between the links and the bridges.
Link receive module.
Link transmit module.
Connection between two HyperTransport™ devices.
Interrupt message type.
Pulldown.
The physical interface layer of the AMD-8132™ tunnel
Polarity.
Pullup.
Interrupt redirection register.
Single Data Rate. This data transfer rate is one time the common clock.
Standard Hot-Plug Controller
Interrupt trigger mode.
®
2.0 Tunnel Data Sheet
®
Mode 2, this data transfer rate is two times the common clock.
Preface
Description
.
26792 Rev. 3.07 July 2005