AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 103

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
IDRDR.
Default: 0000 0000 F800 0001h
HyperTransport™ Revision ID Capability Block
Note:This is the version of the HyperTransport capability block for device B.
Default: A1: 8825 F408h, Bx: 8840 F408h
Chapter 3
15:8
7:0
Bits
63
62
61:56
55:24
23:16
15:8
7
6
5
4:2
1
0
Bits
31:24
Capabilities Pointer. Read Only. Points to the next capability block. The value of this register varies
as follows:
Capability ID. Read only. Specifies this is a HyperTransport™ capabilities block.
Description
IRR. Read. Set by hardware. Cleared by hardware or Write 1 to clear. This bit provides duplicate
access to RDR[IRR] described in section 3.6. However, writing a 1 to this bit clears this register; which
is not the case with RDR[IRR].
PASSPW. Read-Write. The state of this bit is reflected in the PassPW bit of the HyperTransport™ link
interrupt request packet.
Reserved.
INTRINFO[55:24]. Read-Write. IntrInfo[55:24] in the HyperTransport™ link interrupt request packet.
IV. Read-Write. IntrInfo[23:16] in the HyperTransport™ link interrupt request packet; this provides
duplicate access to RDR[IV] described in section 3.6.
DEST. Read-Write. IntrInfo[15:8] in the HyperTransport™ link interrupt request packet; this provides
duplicate access to RDR[DEST] described in section 3.6.
INTRINFO[7]. Read-Write. IntrInfo[7] in the HyperTransport™ link interrupt request packet.
DM. Read-Write. IntrInfo[6] in the HyperTransport™ link interrupt request packet; this provides
duplicate access to RDR[DM] described in section 3.6.
TM. Read-Write. IntrInfo[5] in the HyperTransport™ link interrupt request packet; this provides
duplicate access to RDR[TM] described in section 3.6.
MT. Read-Write. IntrInfo[4:2] in the HyperTransport™ link interrupt request packet. Accesses to
RDR[MT] described in section 3.6. result in translated accesses to this field. See RDR[MT].
POL. Read-Write. This bit provides duplicate access to RDR[POL] described in section 3.6. This bit is
Read Only for IDRDR indices of 0x18, 0x1A, 0x1C (internal interrupts are always active high).
IM. Read-Write. This bit provides duplicate access to RDR[IM] described in section 3.6.
Description
Capability Type. Capability type is Revision ID.
• If Dev[B,A]:0x48[HPEN] = 0, then Dev[B,A]:0xB8[15:8] = C0h (HyperTransport™ capability block).
• If Dev[B,A]:0x48[HPEN] = 1, then Dev[B,A]:0xB8[15:8] = 90h (hot-plug capability block).
AMD-8132™ HyperTransport™ PCI-X
Registers
®
Attribute: See Below
Attribute: Read Only
2.0 Tunnel Data Sheet
DevB:0xC0
103