AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 97

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 3
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SCM_Class 2_ DeviceSpecificError. Read. Write 1 to clear. This bit is set if the AMD-8132™ tunnel
receives a Split Completion Message of Class 2, index 8Xh (Device-Specific Error).
Note: Reset by PWROK, not LDTRESET_L.
DROPPED_MSI. Set by hardware. Read. Write 1 to clear. This bit is set whenever an MSI request is
dropped due to an uncorrectable data error.
Note: Reset by PWROK, not LDTRESET_L.
CLASS2_SCM_ERR_CLEAR. Write Only. Write 1 to clear CLASS2_SCM_ERR bit.
CLASS2_MSG_IDXHI. Read Only. Set by hardware. This register indicates the top three bits of the
message index of the first detected Class 2 split completion message that was not an uncorrectable
split write data error. If Dev[B,A]:0x80[CLASS2_SCM_ERR] is not asserted, this register is undefined.
Note: Reset by PWROK, not LDTRESET_L.
CLASS2_SCM_ERR. Read. Set by hardware. Write 1 to bit 13 (CLASS2_SCM_ERR_CLEAR) to
clear. A Class 2 (completer error) split completion message was received that was not an
uncorrectable split write data error (the message index did not equal 1). The message index of the first
detected Class 2 split completion message that was not an uncorrectable split write data error is
recorded in Dev[B,A]:0x80[CLASS2_MSG_IDX].
Note: Reset by PWROK, not LDTRESET_L.
CLASS2_MSG_IDXLO. Read Only. Set by hardware. This indicates the bottom five bits of the
message index of the first detected Class 2 split completion message that was not an uncorrectable
split write data error. If Dev[B,A]:0x80[CLASS2_SCM_ERR] is not asserted, this register is undefined.
Note: Reset by PWROK, not LDTRESET_L.
SCM_PAR_ERR. Read. Set by hardware. Write 1 to clear. Cleared by hardware immediately after
assertion if Dev[B,A]:0x48[CLEARPCILOG_L] is asserted (0). This bit is set if the AMD-8132 tunnel
detects an uncorrectable error in the data phase while receiving a split completion message.
Note: Reset by PWROK, not LDTRESET_L.
ADDR_OR_ATTR_ERR. Read. Set by hardware. Write 1 to clear. Cleared by hardware immediately
after assertion if Dev[B,A]:0x48[CLEARPCILOG_L] is asserted (0). This bit is set if the
AMD-8132 tunnel detects an uncorrectable error on the PCI bus during an address or attribute phase.
Note: Reset by PWROK, not LDTRESET_L.
DISCARDED_POST. Read. Set by hardware. Write 1 to clear. Resets to 0. Cleared by hardware
immediately after assertion if Dev[B,A]:0x48[CLEARPCILOG_L] is asserted (0). Indicates the bridge
was forced to discard a posted request it was trying to forward to PCI/PCI-X
master abort, target abort, or uncorrectable data error on the transfer.
Note: Reset by PWROK, not LDTRESET_L.
PERR_OBSERVED. Read. Set by hardware. Write 1 to clear. This bit is set whenever PERR_L is
asserted on PCI-X
equations for the fatal and nonfatal interrupts. See DevA:0xDC and Chapter 5.
Note: This bit is set whenever PERR_L is asserted regardless of whether the AMD-8132 tunnel or another device
asserted it. Reset by PWROK, not LDTRESET_L.
®
bus [B,A] and remains set until cleared by software. This bit is also used in the
AMD-8132™ HyperTransport™ PCI-X
Registers
®
due to receiving a
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2.0 Tunnel Data Sheet
97