AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 96

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

AMD-8132™ HyperTransport™ PCI-X
PCI-X
Default: 0000 0000h
If the Select Secondary ECC Registers bit Dev[B.A]:0x70[0] is cleared, this register displays primary interface
information. If the Select Secondary ECC Registers bit is set, this register displays secondary interface
information. Since the primary interface is not PCI-X, it never receives an ECC error and these registers return
undefined values if the Select Secondary ECC Registers bit is cleared. The description below assumes that the
Select Secondary ECC Registers bit is set.
This register records the contents of the bus during the attribute phase, regardless of the type or length of the
transaction, or the phase in which the error occurred. Registers that store information from the failing
transaction always store information directly from the bus (uncorrected), even if error correction is possible.
This register is Read Only.
Note: This register is cleared by PWROK, not by LDTRESET_L.
Misc Bridge Errors
Default: 0000 0000h
96
Bits
31:20
19
18
17
16
• If the ECC Error Phase register for the PCI bus is non-zero (indicating that an error has been captured), the
• If the ECC Error Phase register is zero, the contents of this register are undefined.
ECC Attribute register indicates the contents of the AD[31:00] bus for the attribute phase of the transaction
that included the error.
®
Description
Reserved.
Primary Signalled Master Abort. Read. Write 1 to clear. This bit is set if the AMD-8132™ tunnel is
the end of chain device and the AMD-8132 tunnel receives a nonposted operation on the
HyperTransport™ bus that goes to the end of chain. This bit exists only in DevA:0x80 and is reserved
in DevB:0x80.
Note: Reset by PWROK, not LDTRESET_L.
PCI Busy Time Out Error. Read. Reset the AMD-8132 tunnel PCI bridge and write 1 to clear. This bit
is set if the AMD-8132 tunnel detects that the PCI-X
asserted) for 49152 PCI clocks.
Note: Reset by PWROK, not LDTRESET_L.
SCM_Class 1_TargetAbortError. Read. Write 1 to clear. This bit is set if the AMD-8132 tunnel
receives a Split Completion Message of Class 1, index 01h (Target Abort).
Note: Reset by PWROK, not LDTRESET_L.
SCM_Class2_ByteCountOutOfRangeError. Read. Write 1 to clear. This bit is set if the AMD-8132
tunnel receives a Split Completion Message of Class 2, index 00h (Byte Count Out of Range).
Note: Reset by PWROK, not LDTRESET_L.
ECC Attribute
®
2.0 Tunnel Data Sheet
Registers
®
bus has been non-idle (FRAME# or IRDY#
26792 Rev. 3.07 July 2005
Attribute: See Below
Dev[B,A]:0x7C
Dev[B,A]:0x80
Chapter 3