AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 133

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 3
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7:0
Trigger Mode [TM]. Read-Write. IntrInfo[5] in the HyperTransport™ link interrupt request packet.
0 = Edge sensitive.
1 = Level sensitive.
Note: Normally, it is expected that this bit be programmed for level-sensitive interrupts. This bit is ignored for
Interrupt Request Receipt [IRR]. Read Only. This bit is not defined for edge-triggered interrupts. For
level-triggered interrupts, this bit is set by the hardware after an interrupt is detected. It is cleared by
receipt of EOI as specified in section 1.3.2.
Polarity [POL]. Read-Write.
Delivery Status [DS]. Read Only.
0 = Idle.
1 = Interrupt message pending.
Destination Mode [DM]. Read-Write. IntrInfo[6] in the HyperTransport™ link interrupt request packet.
0 = Physical mode.
1 = Logical mode.
Message Type [MT]. Read-Write. These bits are physically located in IDRDR[MT], see
Dev[B,A]:0x[BC,B8]. Accesses to this field result in translated accesses to the register bits in
IDRDR[MT]. The value in IDRDR[MT] becomes the IntrInfo[4:2] field in HyperTransport™ link interrupt
request packets. The translation is as follows:
For example: a write of 111b to RDR[MT] results in a write of 110b in IDRDR[MT]. Subsequent reads
of RDR[MT] provide 111b. Subsequent reads of IDRDR[MT] provide 110b. The value placed in link
interrupt request packets is as specified in IDRDR[MT] (110b). A write of 110b in IDRDR[MT] would be
read as 111b through RDR[MT].
Interrupt Vector [IV]. Read-Write. IntrInfo[23:16] in the HyperTransport™ link interrupt request
packet.
• If this is a 0, the interrupt is active high.
• If this is a 1, the interrupt is active low.
• For the RDRs associated with [B,A]PIRQ[D,C,B,A]_L this bit applies to the polarity of the
• For the RDRs associated with the fatal, nonfatal, and SHPC interrupts, this bit is reserved and
Access to RDR[MT]
000b
001b
010b
011b
100b
101b
110b
111b
[B,A]PIRQ[D,C,B,A]_L pins as they enter the AMD-8132 tunnel. Normally, this bit is expected to be
programmed for active low interrupts. This bit has no effect on the NIOAIRQ[D,C,B,A]_L pins.
always 0. These internal interrupts are always active high.
delivery modes of SMI, NMI, Init, and ExtINT, which are always treated as edge sensitive.
Interrupt type
Fixed
Lowest priority
SMI
Reserved
NMI
Init
Reserved
ExtINT
AMD-8132™ HyperTransport™ PCI-X
Registers
Value in IDRDR[MT]
000b
001b
010b
111b
011b
100b
101b
110b
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2.0 Tunnel Data Sheet
133