AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 93

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
Chapter 3
15:8
7
6:4
Syndrome. Read Only. The syndrome indicates information about the bit or bits in error. For 32-bit
transfers, E6 to E0 are the syndrome sequence. For 64-bit transfers, E7 to E0 are the syndrome
sequence. For details see section 5.1.2 of PCI-X Protocol Addendum to the PCI Local Bus Specification,
Rev 2.0a.
Note: This register is cleared by PWROK, not by LDTRESET_L.
ECC Error Corrected. Read Only.
0 = The captured error was not corrected.
1 = The captured error was corrected.
Note: This register is cleared by PWROK, not by LDTRESET_L.
ECC Error Phase. Write 1 to clear.
Note: This register is cleared by PWROK, not by LDTRESET_L.
• If the ECC Error Phase register is non-zero, this bit indicates whether the error that was captured
• If the ECC Error Phase register is zero, this bit is undefined.
• If the bridge detects either a correctable or uncorrectable ECC error, this register indicates in
• If this register is set to 0, the bridge is enabled to latch information about an ECC error. If the
Bit
8
9
10
11
12
13
14
15
was corrected. Correctable ECC errors occurring while the Disable Single-Bit-Error Correction bit
is 0 are the only errors that are corrected.
which phase of the transaction the error occurred. For data phase errors, this register indicates
whether it was a 32-bit data error (7-bit ECC) or 64-bit data error (8-bit ECC).
device detects an error, it latches the phase of the error in this register and stores status
information for the error in the ECC Status, ECC Address, and ECC Attribute registers. Writing a 1
to any of these bits clears this register and enables the bridge to capture the next error.
RegisterECC Error Phase
0
1
2
3
4
5
6
7
Syndrome
E0
E1
E2
E3
E4
E5
E6
E7 for 64-bit data, 0b for 32-bit data
No error
First 32 bits of address
Second 32 bits of address
Attribute phase
32-bit data phase
64-bit data phase
Reserved
Reserved
AMD-8132™ HyperTransport™ PCI-X
Registers
®
2.0 Tunnel Data Sheet
93