AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 21

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
1.3.1
1.3.1.1
Each bridge contains a PCI/PCI-X arbiter with five request/grant pairs available for each bus. Only a subset of
these request/grant pairs are available for hot-plug, 66 MHz PCI, PCI-X Mode 1, or PCI-X Mode 2 operation.
See section 4.2.3 for more details.
Depending on the current mode of the bus, the arbiter operates as a conventional PCI arbiter, a PCI-X Mode 1
arbiter, or a PCI-X Mode 2 arbiter. In PCI-X Mode 2 there are CSRs controlling the number of idle cycles
before the arbiter goes into low-power mode. See section 3.2, Dev[B,A]:0x48.
The arbiter arbitrates between the external requests, represented by [B,A]_REQ_L[4:0], and internal requests.
Internal requests are generated when:
When no internal or external requests are asserted to the arbiter, it parks (asserts a grant) to one master in order
to keep the bus from floating. The choice of master is controlled by Dev[B,A]:0x48[PARKATHOST].
1.3.1.2
An external arbiter can be used in all PCI and PCI-X modes except for PCI-X Mode 2. The internal arbiter for
the AMD-8132 tunnel can be disabled and an external customer-supplied arbiter used instead. Disabling the
internal arbiter can be done on a per PCI bus basis using the setting for EXTARB_L at Dev[B,A]:0x48
In external arbiter mode, the AMD-8132 tunnel produces a non-preemptable and a preemptable request.
1.3.2
The AMD-8132 tunnel has capabilities to handle internal and external interrupts. It contains a standard
IOAPIC and can accept Message Signalled Interrupts (MSIs) from the PCI buses. Incoming interrupts can
result in HyperTransport interrupt packets, HyperTransport virtual wire packets, or assertions of the NIOAIRQ
pins. Figure 3 shows interrupt routing possibilities.
Chapter 1
• A HyperTransport operation is accepted by the bridge and will be forwarded to the PCI bus (the bridge
• A hot-plug command occurs which requires the SHPC to own the PCI bus.
• A non-preemptable request is a request to own the PCI bus for hot-plug. Once asserted, the external arbiter
• A preemptable request is a request to own the PCI bus for normal usage. The preemptable request and
wants to be master on the PCI bus).
must keep its non-preemptable grant asserted until the AMD-8132 tunnel deasserts its non-preemptable
request. The external arbiter should not park the bus on this grant line. The non-preemptable request comes
out on the signal [B,A]_GNT_L1. The non-preemptable grant from the external arbiter is driven to the
AMD-8132 tunnel on the signal [B,A]_REQ_L1. If this bus is not enabled for hot-plug, the non-
preemptable request/grant lines do not need to be implemented and this grant line should be pulled high.
grant behave as normal PCI or PCI-X request and grant signals. The preemptable request comes out on the
signal [B,A]_GNT_L0. The preemptable grant from the external arbiter is driven to the AMD-8132 tunnel
on the signal [B,A]_REQ_L0.
Arbiters
Internal Arbiters
External Arbiters
Interrupts
Functional Operation
AMD-8132™ HyperTransport™ PCI-X
®
2.0 Tunnel Data Sheet
.
21