AMD-8132BLCT AMD (ADVANCED MICRO DEVICES), AMD-8132BLCT Datasheet - Page 29

• Manufacturer Part Number: AMD-8132BLCT
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-8132BLCT

• Lead Free Status / RoHS Status: Not Compliant

26792 Rev. 3.07 July 2005
The following comparisons show the relationship between PCI-X transactions in which the relaxed ordering
bit is set and link packets:
1.3.6.4
The following apply to AMD-8132 tunnel downstream transactions:
Chapter 1
• Upstream PCI-initiated memory writes which include no valid byte enables complete normally over the
• Secondary bus configuration cycles are never claimed by the AMD-8132 tunnel; including configuration
• PCI-X Device ID Messages (DIMs) are never claimed by the AMD-8132 tunnel.
• For each bridge, up to 27 nonposted requests to the link may be outstanding at a given time. Based on the
• The HyperTransport coherent bit in upstream requests is always set for interrupt requests (including MSI/
• Downstream special cycles that are encoded in configuration cycles to device 31 of the bridge secondary
• In the translation from type 1 HyperTransport link configuration cycles to secondary bus type 0
The UnitID associated with the bridge is also returned in the response to upstream requests and is used to
determine the destination of the response (bridge A or bridge B).
PCI bus. However, the transaction may be dropped by the AMD-8132 tunnel resulting in no corresponding
HyperTransport link transactions. This does not apply to I/O transactions.
cycles to device 31 in which special cycles are encoded per the PCI-to-PCI Bridge Architecture
Specification, Rev 1.2.
state of Dev[B,A]:0x40[NZSEQID], the AMD-8132 tunnel may or may not generate non-zero SeqID
values in the upstream link requests that result from external PCI/PCI-X master read requests. Up to 8
outstanding PCI/PCI-X read sequences can be active at one time. If enabled, each outstanding secondary
read sequence is assigned a unique SeqId from 8h to Fh. All bridge-sourced transactions are compliant to
PCI or PCI-X ordering rules. As PCI or PCI-X transactions are converted to link transactions, they are
translated as described in HyperTransport™I/O Link Specification, Rev 2.0.
MSI-X transactions) and all requests from the secondary bus when it is in PCI mode. If the secondary bus
is in PCI-X mode, the HyperTransport coherent bit is the inverse of the no snoop bit from the PCI-X
request.
bus number (per the PCI-to-PCI Bridge Architecture Specification, Rev 1.2) are translated to special cycles
on the PCI bus.
configuration cycles, the AMD-8132 tunnel converts the device number to an IDSEL AD signal as
follows: device 0 maps to AD[16]; device 1 maps to AD[17]; and so forth. Device numbers 16 through 31
Upstream PCI-X
A memory write request in which the relaxed
ordering bit of the attribute field is set.
A read request in which the relaxed ordering bit of
the attribute field is set.
Any response to a downstream link read request in
which bit[3] of the command field (response may
pass posted write) is set.
or memory spaces; configuration space windows defined in the configuration registers of the bridge;
and the base address register spaces defined by the bridge.
Downstream Transactions
®
2.0 Transaction
Functional Operation
AMD-8132™ HyperTransport™ PCI-X
Corresponding Link Transaction
PassPW is set in the request.
Bit[3] of the command field (response may pass
posted write) in the read request is set.
PassPW is set in the response.
®
2.0 Tunnel Data Sheet
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