XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 106

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Chapter 3: Phase-Matched Clock Dividers (PMCDs)
Application Examples
106
DCM and a Single PMCD
DCM and Parallel PMCDs
PMCD to BUFGCTRL
PMCD to PMCD
A PMCD can drive any BUFGCTRL in the same top/bottom half of the chip.
A dedicated local connection exists from the CLKA1D8 output of each PMCD to the CLKA
input of any other PMCD within the same tile (group of two).
The Virtex-4 FPGA PMCD can be used in a variety of creative and useful applications. The
following examples show some of the common applications.
A PMCD can be connected to a DCM to further divide a DCM clock.
this example. Note the following guidelines:
•
•
A DCM can be connected to parallel PMCDs.
following guidelines:
•
•
Reset
The DCM feedback (CLKFB) must be driven by the same frequency as CLKIN for 1X
feedback. Therefore, the PMCD output corresponding to CLK0 must be used to drive
the CLKFB pin.
The RST_DEASSERT_CLK attribute must be set to the PMCD input driven by CLK0.
♦
The DCM feedback (CLKFB) must be driven by the same frequency as CLKIN for 1X
feedback. Therefore, the PMCD output corresponding to CLK0 must be used to drive
the CLKFB pin.
The RST_DEASSERT_CLK attribute must be set to the PMCD input driven by CLK0.
♦
When a DCM is connected to a PMCD, all output clocks, except CLK0 and
CLK2X, are held Low until LOCKED is High. Therefore, setting
RST_DEASSERT_CLK to the corresponding DCM feedback clock ensures a
completed feedback loop. Note: CLK2X feedback is not supported.
When a DCM is connected to a PMCD, all output clocks, except CLK0 and
CLK2X, are held Low until LOCKED is High. Thus, setting RST_DEASSERT_CLK
CLKIN
CLKFB
RST
DCM
LOCKED
CLK2X
Figure 3-7: DCM and a Single PMCD
www.xilinx.com
CLK0
RST_DEASSERT_CLK = CLKA
EN_REL = FALSE
Reset
Figure 3-8
CLKA
CLKB
RST
REL
PMCD
illustrates this example. Note the
CLKA1D2
CLKA1D4
UG070 (v2.6) December 1, 2008
CLKA1
CLKB1
Virtex-4 FPGA User Guide
Figure 3-7
BUFGs
UG070_3_07_071404
illustrates
f/1
f/2
f/4
2f
R